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PDF PC33888APNB Data sheet ( Hoja de datos )

Número de pieza PC33888APNB
Descripción Quad High-Side and Octal Low-Side Switch for Automotive
Fabricantes Motorola Inc 
Logotipo Motorola  Inc Logotipo



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No Preview Available ! PC33888APNB Hoja de datos, Descripción, Manual

MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Document order number: MC33888
Rev 3.0, 10/2004
Product Preview
Quad High-Side and Octal Low-Side
Switch for Automotive
The 33888 is a single-package combination of a power die with four
discrete high-side MOSFETs (two 10 mand two 40 mΩ) and an integrated
IC control die consisting of eight low-side drivers (600 meach) with
appropriate control, protection, and diagnostic features.
Programming, control, and diagnostics are accomplished using a 16-bit SPI
interface. Additionally, each high-side output has its own parallel input for
pulse-width modulation (PWM) control if desired. The low sides share a single
configurable direct input.
The 33888 is available in two power packages.
Features
• Dual 10 mHigh Side, Dual 40 mHigh Side, Octal 600 mLow Side
• Full Operating Voltage of 6.0 V to 27 V
• SPI Control of High-Side Overcurrent Limit, High Side Current Sense,
Output OFF Open Load Detection, Output ON/OFF Control, Watchdog
Timeout
• SPI Reporting of Program Status and Fault
• High-Side Analog Current Feedback with Selectable Ratio
• Enhanced 16 V Reverse Polarity VPWR Protection
33888
33888A
SOLID STATE RELAY FOR
AUTOMOTIVE APPLICATIONS
Bottom View
PNB SUFFIX
APNB SUFFIX
CASE 1438-06
36-TERMINAL PQFN
(12 x 12)
Top View
FB SUFFIX
CASE 1315-03
64-TERMINAL PQFP
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
PC33888PNB/R2
PC33888APNB/R2
-40°C to 125°C
36 PQFN
MC33888FB/R2
64 PQFP
+5.0 V
33888 Simplified Application Diagram
VPWR
+5.0 V
8 x Relay or LED
4
MCU
A/D
A/D
4
33888
FS VDD
VPWR
IHS0:IHS3
ILS
LS4:LS11
RST
SPI HS3
WDIN
HS2
CSNS2-3
CSNS0-1
FSI GND
HS1
HS0
Loads
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Motorola, Inc. 2004
For More Information On This Product,
Go to: www.freescale.com

1 page




PC33888APNB pdf
Freescale Semiconductor, Inc.
TERMINAL DEFINITIONS FOR PQFN (continued)
Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on
page 19.
Terminal
Terminal
Name
Formal Name
Definition
34 RST
Reset (Active Low)
This input terminal is used to initialize the device configuration and fault registers,
as well as place the device in a low current standby mode. This terminal also starts
the watchdog timeout when transitioned from logic [0] to logic [1]. This terminal
should not be allowed to be at logic [1] until VDD is in regulation. This input has an
internal passive pulldown.
35 FSI
Fail-Safe Input
The Fail-Safe input terminal level determines the state of the outputs after a
watchdog timeout occurs. This terminal has an internal pullup. If the FSI terminal is
left to float to a logic [1], then HS0 and HS2 will turn on when in the Fail-Safe state.
If the FSI terminal is tied to GND, the watchdog circuit and fail-safe operation will be
disabled, thus allowing operation without a watchdog signal.
36 WDIN
Watchdog Input
This input terminal is a CMOS logic level input that is used to monitor system
operation. If the incoming watchdog signal does not transition within the normal
watchdog timeout range, the device will operate in the Fail-Safe mode. This input
has an active internal pulldown.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
33888
5

5 Page





PC33888APNB arduino
Freescale Semiconductor, Inc.
STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 6.0 V VPWR 27 V, 4.5 V VDD 5.5 V, -40°C TJ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min Typ Max Unit
POWER INPUT
Supply Voltage Range
Fully Operational
VPWR
V
6.0 – 27
VPWR Supply Current
TJ > 125°C
TJ 125°C
IPWR(ON)
mA
– 17 25
– – 20
VPWR Standby Current (All Outputs OFF, Open Load Detection Disabled,
WAKE = H, RST = H)
TJ > 125°C
TJ 125°C
IPWR(SBY)
mA
– 4.2 7.0
– 2.9 5.0
Sleep State Supply Current (VPWR < 12.6 V, RST < 0.5 V, WAKE < 0.5 V,
HS[0:3] = 0 V) (Note 11)
TJ = 85°C
TJ = 25°C
IPWR(SS)
µA
– – 80
– 1.0 25
Logic Supply Voltage Range
VDD
4.5 5.0 5.5 V
Logic Supply Current
TJ > 125°C
TJ 125°C
IDD(ON)
mA
– 4.2 7.0
– 2.9 5.0
Logic Supply Sleep State Current
IDD(SS)
– – 5.0 µA
Sleep State Low-Side Output Leakage Current (per Low-Side Output,
RST = LOW)
TJ = 85°C
TJ = 25°C
ISLK(SS)
µA
– – 3.0
– – 1.0
Overvoltage Shutdown Threshold
VPWROV
28.5 32
36 V
Overvoltage Shutdown Hysteresis
VPWROV(HYS)
0.2
0.6
1.5 V
Undervoltage High-Side Output Shutdown (Note 12)
VPWRUV
5.0 5.6 6.0 V
Undervoltage Low-Side Output Shutdown
APNB Suffix Only (Note 12)
PNB and FB Suffixes
VPWRUV
V
3.0 4.0 4.4
5.0 5.6 6.0
Undervoltage High-Side Shutdown Hysteresis
VPWRUV(HYS)
0.1
0.3
0.5 V
Notes
11. This parameter is tested at 125°C with a maximum value of 10 µA.
12. SPI/IO and internal logic operational. Outputs will recover in instructed state when VPWR voltage level returns to normal as long as the level
does not go below VPWRUV.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
33888
11

11 Page







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