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PDF QL2009-0PB256I Data sheet ( Hoja de datos )

Número de pieza QL2009-0PB256I
Descripción 3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility
Fabricantes ETC 
Logotipo ETC Logotipo



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No Preview Available ! QL2009-0PB256I Hoja de datos, Descripción, Manual

QL2009
3.3V and 5.0V pASIC® 2 FPGA
Combining Speed, Density, Low Cost and Flexibility
Rev. C
pASIC 2
HIGHLIGHTS
… 9,000
usable ASIC gates,
225 I/O pins
QL2009
Block Diagram
Ultimate Verilog/VHDL Silicon Solution
-Abundant, high-speed interconnect eliminates manual routing
-Flexible logic cell provides high efficiency and performance
-Design tools produce fast, efficient Verilog/VHDL synthesis
Speed, Density, Low Cost and Flexibility in One Device
-16-bit counter speeds exceeding 200 MHz
-9,000 usable ASIC gates, 16,000 usable PLD gates, 225 I/Os
-3-layer metal ViaLink® process for small die sizes
-100% routable and pin-out maintainable
Advanced Logic Cell and I/O Capabilities
-Complex functions (up to 16 inputs) in a single logic cell
-High synthesis gate utilization from logic cell fragments
-Full IEEE Standard JTAG boundary scan capability
-Individually-controlled input/feedback registers and OEs on all I/O pins
Other Important Family Features
-3.3V and 5.0V operation with low standby power
-I/O pin-compatibility between different devices in the same packages
-PCI compliant (at 5.0V), full speed 33 MHz implementations
-High design security provided by security fuses
3
672
Logic
Cells
3-35

1 page




QL2009-0PB256I pdf
QL2009
PINOUT DIAGRAM
256-PIN PBGA
pASIC
QL2009-1PB256C
TOP
19 17 15 13 11 9 7 5 3 1
PIN A1
CORNER
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
BOTTOM
3
3-39

5 Page





QL2009-0PB256I arduino
QL2009
Clock Cells
Symbol
tACK
tGCKP
tGCKB
Parameter
Array Clock Delay
Global Clock Pin Delay
Global Clock Buffer Delay
Propagation Delays (ns)
Loads per Half Column [10]
1 2 3 4 8 10 13
2.2 2.2 2.3 2.4 2.5 2.6
1.2 1.2 1.2 1.2 1.2 1.2 1.2
1.5 1.6 1.6 1.7 1.8 1.9 2.0
I/O Cells
Propagation Delays (ns)
Symbol
Parameter
Fanout [8]
1 2 3 4 8 10
tI/O Input Delay (bidirectional pad)
1.8 2.1 2.4 2.7 3.9 4.6
tISU Input Register Set-Up Time
4.8 4.8 4.8 4.8 4.8 4.8
tIH Input Register Hold Time
0.0 0.0 0.0 0.0 0.0 0.0
tlOCLK Input Register Clock To Q
0.8 1.1 1.4 1.7 2.9 3.6
tlORST Input Register Reset Delay
0.7 1.0 1.3 1.6 2.8 3.5
tlESU
Input Register clock Enable Set-Up Time 4.1 4.1 4.1 4.1 4.1 4.1
tlEH
Input Register Clock Enable Hold Time
0.0 0.0 0.0 0.0 0.0 0.0
3
Symbol
Parameter
tOUTLH
tOUTHL
tPZH
tPZL
tPHZ
tPLZ
Output Delay Low to High
Output Delay High to Low
Output Delay Tri-state to High
Output Delay Tri-state to Low
Output Delay High to Tri-State [11]
Output Delay Low to Tri-State [11]
Propagation Delays (ns)
Output Load Capacitance (pF)
30 50
75 100 150
2.6 3.0 3.6 4.1 5.2
2.8 3.3 3.9 4.5 5.7
2.1 2.6 3.1 3.7 4.8
2.6 3.3 4.1 4.9 6.5
2.9
3.3
Notes:
[10] The array distributed networks consist of 48 half columns and the global distributed networks consist of
52 half columns, each driven by an independent buffer. The number of half columns used does not affect
clock buffer delay. The array clock has up to 10 loads per half column. The global clock has up to 13
loads per half column.
[11] The following loads are used for tPXZ:
1K
tPHZ
5 pF
1K
tPLZ
5 pF
3-45

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