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PDF RC56SP-USB Data sheet ( Hoja de datos )
| Número de pieza | RC56SP-USB | |
| Descripción | INTEGRATED V.90/K56FLEX MODEM DEVICE SETS WITH USB INTERFACE FOR DESKTOP APPLICATIONS | |
| Fabricantes | ETC | |
| Logotipo |  |
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Introduction
The CONEXANT™ RC56D Modem Device Set supports
the USB (Universal Serial Bus), as described by the
Universal Serial Bus Specification Revision 1.0. USB
provides a flexible interconnect between a PC and a wide
range of peripherals, such as to a CONEXANT modem
device set.
The CONEXANT RC56D family devices, in conjunction
with the R8292 USB controller provide a complete USB
modem solution. The supported modem feature set for the
USB modem solution is the same as the standard RC56D
parallel host interface device set (see “RC56D and
RC336D Integrated V.90/K56flex/V.34 Modem Device Set
for Desktop Applications” Data Sheet, Order No. MD211).
The modem models, which include the R8292 UCU (USB
Controller Unit in 68-PLCC), are listed in Table 1.
Hardware
A complete accelerator kit implementing the USB solution
is offered as “Perth” (AK56-D540). This design consists of
the RC56D parallel host interface device set and the
R8292 USB Controller Unit (UCU). The R8292 operates
with a 12 MHz crystal. A 32K x 8, 150 ns EEPROM is
required for USB controller firmware. Additionally, one
latch, one transistor, and two bus transceivers are
required.
The R8292 USB Controller is based on the MCS®51
microcontroller. It is a hubless USB peripheral controller
that supports suspend/resume modes and
isochronous/non-isochronous transfers.
Firmware
Firmware for the R8292 controller is provided in object
form, however, vendor specific descriptors can be
customized with a supplied utility. Vendor ID, Product ID,
Device Release Number, Manufacturer Name, Product
Name, and Serial Number can all be modified.
Drivers
A complete set of software drivers is provided for
Windows 98 and Windows 95 OSR 2.1 support. Sample
INF files are also provided.
Features
• All features supported by the RC56D family (see data
sheet Order No. MD211)
• Universal Serial Bus Specification Rev 1.0 compliant
• Three function endpoint pairs with corresponding
transmit/receive FIFO pairs
• Automatic transmit/receive FIFO management
• USB full speed 12Mbps
• USB low speed 1.5Mbps
• Reset separation
• Four LED driver outputs
• On-chip phase-locked loop (PLL)
• On-chip USB transceivers
• 256 bytes on-chip Data RAM
• Suspend/Resume
• Vendor specific descriptors
• Windows 98 support
• Windows 95 OSR 2.1 support
• Extension pickup/remote hang-up detection
• Line-in-use detection
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Signal Name
Type
ALE O
AVCC
DM0, DP0
PWR
I/O
EA# I
ECAP
I
FSSEL
INT1#
I
I
INT0#
LED3:0
OVRI#/P3.0
I
O
I
P0.7:0
I/O
P1.7
P1.6
P1.5
P1.4
P1.3
I/O
O
O
O
O
P1.2
P1.1
P1.0
P2.7:0
P3.5
P3.4
PLLSEL
PSEN#
RD#
RST
O
I/O
I/O
O
I/O
I/O
I
O
O
I
SOF#/P3.1 O
Table 2. R8292 68-Pin PLCC Pin Signal Descriptions
Description
Address Latch Enable. ALE signals the start of an external bus cycle and indicates that valid address
information is available on lines A15:8 and AD7:0. An external latch can use ALE to demultiplex the address
from the address/data bus.
Analog VCC. AVCC input for the phase locked loop circuitry.
USB Port 0. DP0 and DM0 are the differential data plus and data minus signals of USB port 0, the upstream
differential port. These lines do not have internal pullup resistors. Provide an external 1.5 KΩ pullup resistor
at DP0. If DP0 is not pulled high, a continuous SEO (USB reset) will be applied to these inputs causing the
8x931 to stay in reset.
External Access. Directs program memory accesses to on-chip or off-chip code memory. For EA# strapped
to ground, all program memory accesses are off-chip. For EA# strapped to VCC , program accesses on-chip
ROM if the address is within the range of the on-chip ROM; otherwise the access is off-chip. The value of
EA# is latched at reset. For devices without on-chip ROM, EA# must be strapped to ground.
External Capacitor. Connect a 2.2 µF capacitor between this pin and VSS to ensure proper operation of the
differential line drivers.
Full Speed Select. Connect to VCC for 12MHz Xtal and 12Mbps full speed USB rate.
HINT. Host bus interrupt input is set high by MCU when the MCU receiver error flag, received data available,
transmitter holding register empty, or modem status interrupt is asserted.
RINGWAKE. Used to notify the host of an incoming ring in order to come out of suspend mode.
LED Drivers. Designed to drive LEDs connected directly to VCC. NC.
Overcurrent Sense. Sense input to indicate an overcurrent condition on an external down-stream port.
Active low with an internal pullup. NC.
Address/Data Lines. Eight-bit, open-drain, bidirectional I/O lines with Schmitt trigger inputs that represent
lower byte of external memory address multiplexed with data.
NC. Quasi-bidirectional I/O port with internal pullup.
Ready Indicate. Active low output to drive READY LED. Port has internal pullup.
DCD Indicate. Active low output to drive DCD LED. Port has internal pullup.
DATA Indicate. Active low output to drive DATA LED. Port has internal pullup.
MODEMPWRCNTRL. Active low output used to control power supply to non-USB side of isolation. Port has
internal pullup.
MDMRESET. Active low output used to reset the MCU and MDP. This port has an internal pullup.
NC. Quasi-bidirectional I/O port with internal pullup.
NC. Quasi-bidirectional I/O port with internal pullup.
Address Lines. Eight-bit port with internal pullups used for upper byte of external memory address.
NC. Quasi-bidirectional I/O port with internal pullup.
NC. Quasi-bidirectional I/O port with internal pullup.
Phase-locked Loop Select. Connect to VCC for 12MHz Xtal and 12Mbps full speed USB rate.
Program Store Enable. Read signal output. Asserted for read accesses to external program memory.
Read. Asserted for read accesses to external data memory.
Reset. Reset input to the chip. Holding this pin high for 64 oscillator periods while the oscillator is running
resets the device. The port pins are driven to their reset conditions when a voltage greater than VIH1 is
applied, whether or not the oscillator is running. This pin has an internal pulldown resistor which allows the
device to be reset by connecting a capacitor between this pin and VCC.
Asserting RST when the chip is in idle mode or powerdown mode returns the chip to normal operation.
Start of Frame. Start of frame pulse. Active low. Asserted for 8 states when frame timer is locked to USB
frame timing and SOF token or artificial SOF is detected. NC.
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Endpoint Descriptor
Each endpoint used for an interface has its own descriptor, which contains the information required by the host to determine
the bandwidth requirements of each endpoint (see Table 6). An endpoint descriptor, like an Interface Descriptor, is always
returned as part of a configuration descriptor. The default values are:
Bulk In 1: 07058102100000
Bulk Out 1: 07050102100000
Bulk In 2: 07058203080064
Bulk Out 2: 07050202080000
Offset
0
1
2
Field
bLength
bDescriptorType
bEndpointAddress
3 bmAttributes
4 wMaxPacketSize
6 bInterval
Size
1
1
1
1
2
1
Table 6. Endpoint Descriptors
Value
Description
Number
Constant
Endpoint
Bit Map
Number
Number
Size of this descriptor in bytes.
ENDPOINT Descriptor Type.
The address of the endpoint on the USB device described by this
descriptor. The address is encoded as follows:
Bit 0..3: The endpoint number
Bit 4..6: Reserved, reset to 0
Bit 7: Direction, ignored for control endpoints
0 OUT endpoint
1 IN endpoint
This field describes the endpoint’s attributes when it is configured using
the bConfigurationValue.
Bit 0..1: Transfer Type
00 Control
01 Isochronous
10 Bulk
11 Interrupt
All other bits are reserved
Maximum packet size this endpoint is capable of sending or receiving
when this configuration is selected.
For isochronous endpoints, this value is used to reserve the bus time in
the schedule, required for the per frame data payloads. The pipe may,
on an ongoing basis, actually use less bandwidth than that reserved.
The device reports, if necessary, the actual bandwidth used via its
normal, non-USB defined mechanisms.
For interrupt, bulk, and control endpoints smaller data payloads may be
sent, but will terminate the transfer and may or may not require
intervention to restart. Refer to Chapter 5 for more information.
Interval for polling endpoint for data transfers. Expressed in
milliseconds.
This field is ignored for bulk and control endpoints. For isochronous
endpoints this field must be set to 1. For interrupt endpoints, this field
may range from 1 to 255.
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