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PDF PBL40215 Data sheet ( Hoja de datos )
| Número de pieza | PBL40215 | |
| Descripción | RF Transceiver circuit for the Digital Enhanced Cordless Telecommunications (DECT) system | |
| Fabricantes | Ericsson | |
| Logotipo |  |
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Preliminary
JaPnuBaLry420020115
PBL 402 15
RF Transceiver circuit for the Digital
Enhanced Cordless Telecommunications
(DECT) system
Description.
Key features.
The PBL 402 15 is a complete RF transceiver to be used in the Digital Enhanced
Cordless Telecommunications ( DECT ) system. It is designed to interface to various
base-band controllers.
The circuit contains transmit and receive functions that share integrated high stability
VCO´s and a phase locked loop function ( PLL ). All functionality is controlled through a
3-wire bus interface with optional hard wire lines.
The receive section comprises of a low noise image reject down conversion to the
first intermediate frequency, an external channel filter, a second down convertion to a
second intermediate frequency, an integrated channel pass filter, a high gain limiting
amplifier, a received signal strenght indicator with DC compensation loop, a self aligned
frequency discriminator and a preamble based data slicer.
The transmit section comprises of a signal gate and a pre-power amplifier. Data
transmission is achieved by direct open loop modulation of the Tx VCO.
• High Tx output power to +7dBm
• Integrated PLL and high stability
VCO´s
• 3-line serial interface bus
• Minimum 2.7 V supply voltage
• Low current consumption
• Differential Rx input and Tx output
• Flexible interface to various base-
band controllers
• Exellent performance with Ericsson´s
power amplifier PBL403 09
• Low cost
Applications:
• DECT Handset and base station
• Wireless local area network ( WLAN )
• Wireless local loop ( WLL )
Figure 1. Block diagram.
PBL 402 15
Figure 2. Package outlook.
1
1 page  
PBL 402 15
Pin Descriptions (cont.):
Pin number
Name
24 GndRSSI
Function
Ground connection to the RSSI.
Schematic in/output of the pin
A diode to GndFM and GndIF
VCCRF
25
PA Gate
Output control signal for external PA power on/off. PA - Gate
26 IFIN-
27 IFIN+
28 GndIF
29 VCCIF
30 LD
31
32
33, 36
37, 40
34
35
IFOUT-
IFOUT+
GndRF
RX-
RX+
38 TX-
39 TX+
41 VCCRF
Rx IF inputs to internal channel filtering, limiting
amplifiers,RSSI and FM discriminator. Internally
matched to 300 Ω.
Ground connection to the down IF convertor and
channel filter sections.
Voltage supply to the down IF convertor and
channel filter sections.
Lock detect.
GndRF
VCCIF
IFIN-/IFIN+
both inputs alike
GndIF
A diode to GndFM and GndIF
Clamp to GndIF
VCCRF
LD
Rx IF outputs to external adjacent channel filter.
Internally matched to 300Ω.
GndRF
VCCRF
IFOUT-/IFOUT+
both outputs alike
Ground connection to the RF sections.
RF inputs to LNA and image reject mixer.
Internally matched to 100Ω.
Tx outputs to external PA. Internally matched to
100 Ω. Each output requires an externalchoke
to VCC.
Voltage supply to the RF sections.
GndRF
A diode to GndIF and GndPLL
VCCRF
RX-/RX+
both inputs alike
GndRF
VCCRF
TX-/TX+
Both inputs alike
GndRF
Clamp to GndRF
VCCPLL
42
GATE
Input to gate the Tx output power.
43 D
Serial interface, Data .
GATE
GndPLL
VCCPLL
D
GndPLL
Bias
Bias
5
5 Page 
PBL 402 15
Word A Table.
Data address
D0
Name
CE
Default
0
D1 CL
0
D2
CNT_A0
0
D3
CNT_A1
0
D4
CNT_A2
0
D5
CNT_A3
0
D6
CNT_A4
0
D7
CNT_M
0
D8
CNT_R
0
D9 (a) 0
D10
(a)
0
D11
RXVCO_EN
0 (1)
D12
(a)
0
D13
(a)
0
D14
TXVCO_EN
0 (1)
D15
Reserved
0
D16 DRX_T 0
D17 TX_P0
D18 TX_P1
0
0
D19 RX_G
0
D20 IFT0
D21 IFT1
D22 IFT2
a. Use ´0´ only.
b. Recommended at all times.
1
1
0
Description
0 = Chip disable
1 = Chip enable
Active low on the external EN pin will also enable the chip
0 = Internal control flags
1 = External control lines
Synthesiser frequency counter A bit 0 (LSB) to 4 (MSB)
Synthesiser frequency counter M
0 → M = 32 (used for receive)
1 → M = 34 (used for transmit)
Synthesiser reference counter R
0 → R = 6 used if REF = 10.368 MHz
1 → R = 8 used if REF = 13.824 MHz
Receiver VCO enable . 000 = VCO disabled.
Any other setting activates the VCO. (default 100)
Transmit VCO enable . 000 = VCO disabled.
Any other setting activates the VCO. (default 100)
(a)
1 = Analog signal output at DRX pin.
0 = Digital data output at DRX pin.
Transmit power trim bits
0 (LSB) to 1 (MSB)
00 = -1.3 dB Min.
01 = Nominal power
10 = +1.3 dB
11 = +1.9 dB Max.
IRRX gain.
0 = +0dB extra
1 = +9dB extra
Demodulation IF frequency trim bits 0 (LSB) to 2 (MSB).
This should be programmed to the default settings.
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet PBL40215.PDF ] | |
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