DataSheet.es    


PDF PBL386502SHT Data sheet ( Hoja de datos )

Número de pieza PBL386502SHT
Descripción Subscriber Line Interface Circuit
Fabricantes Ericsson 
Logotipo Ericsson Logotipo



Hay una vista previa y un enlace de descarga de PBL386502SHT (archivo pdf) en la parte inferior de esta página.


Total 16 Páginas

No Preview Available ! PBL386502SHT Hoja de datos, Descripción, Manual

June 1999
PBL 386 50/2
Subscriber Line
Interface Circuit
Description
The PBL 386 50/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated
circuit for use in Central Office Metering applications and other telecommunications
equipment. The PBL 386 50/2 has been optimized for low total line interface cost and
a high degree of flexibility in different applications.
The PBL 386 50/2 emulates resistive loop feed, programmable between 2x50
and 2x900 , with short loop current limiting adjustable to max 45 mA. In the current
limited region the loop feed is nearly constant current with a slight slope
corresponding to 2x30k.
A second, lower battery voltage may be connected to the device to reduce short
loop power dissipation. The SLIC automatically switches between the two battery
supply voltages without need for external components or external control.
The SLIC incorporates loop current, ground key and ring trip detection functions.
The PBL 386 50/2 is compatible with both loop and ground start signaling.
Two- to four-wire and four- to two-wire voice frequency (VF) signal conversion is
accomplished by the SLIC in conjunction with either a conventional CODEC/filter or
with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable
two-wire impedance, complex or real, is set by a simple external network.
Longitudinal voltages are suppressed by a feedback loop in the SLIC and the
longitudinal balance specifications meet Bellcore TR909 requirements.
The PBL 386 50/2 package options are 24-pin SSOP, 24-pin SOIC or 28-pin PLCC.
DT
DR
TIPX
RINGX
HP
VCC
VBAT2
VBAT
AGND
BGND
Two-wire
Interface
Ring Trip
Comparator
Ground Key
Detector
Line Feed
Controller
and
Longitudinal
Signal
Suppression
Off-hook
Detector
VF Signal
Transmission
Ring Relay
Driver
Input
Decoder
and
Control
RRLY
C1
C2
C3
DET
POV
PSG
PLC
LP
PLD
REF
VTX
RSN
Key Features
• 24-pin SSOP package
• Programmable two-wire signal
headroom for 2.2 Vrms metering
• High and low battery with automatic
switching
• Only +5 V feed in addition to battery
• Selectable transmit gain (0.5x or 0.25x)
• 70 mW on-hook power dissipation in
active state
• On-hook transmission
• Long loop battery feed tracks Vbat for
maximum line voltage
• No power-up sequence
• 43V open loop voltage @
-48V battery feed
• Constant loop voltage for line leakage
<5 mA (RLeak ~ >10 k@ -48V)
• Full longitudinal current capability
during on-hook state
• Analog over temperature protection
permits transmission while the
protection circuit is active
• Line voltage measurement
• Polarity reversal
• Ground key detector
• Tip open state with ring ground
detector
PBL 386 50/2
Figure 1. Block diagram.
PTG
24-pin SOIC, 24-pin SSOP, 28-pin PLCC
1

1 page




PBL386502SHT pdf
PBL 386 50/2
Parameter
Four-wire to two-wire, g4-2
Four-wire to four-wire, g4-4
Insertion loss
Two-wire to four-wire, G2-4
Four-wire to two-wire, G4-2
Gain tracking
Two-wire to four-wire
Four-wire to two-wire
Noise
Idle channel noise at two-wire
(TIPX-RINGX) or four-wire (VTX) output
Harmonic distortion
Two-wire to four-wire
Four-wire to two-wire
Battery feed characteristics
Loop current, IL , in the current
limited region, reference A, B & C
Tip open state TIPX current, ILeak
Tip open state RINGX current, ILRTo
Tip open state RINGX voltage, VRTo
Ref
fig Conditions
6 relative to 0 dBm, 1.0 kHz. EL=0 V
0.3 kHz < f < 3.4 kHz
f = 8 kHz, 12 kHz,
16 kHz
6 relative to 0 dBm, 1.0 kHz, EL=0 V
0.3 kHz < f < 3.4 kHz
6 0 dBm, 1.0 kHz, Note 5
V
G = 20 · Log TX ; E = 0
V2-4 RX
TR
PTG = AGND
6 0 dBm, 1.0 kHz, Note 6
G4-2 = 20 · Log
VTR
ERX
; EL = 0
6 Ref. -10 dBm, 1.0 kHz, Note 7
-40 dBm to +3 dBm
-55 dBm to -40 dBm
6 Ref. -10 dBm, 1.0 kHz,
-40 dBm to +3 dBm
-55 dBm to -40 dBm
C-message weighting, 2 wire
Psophometrical weighting, 2 wire
C-message weighting, 4 wire
Psophometrical weighting, 4 wire
Note 8
6 0 dBm
0.3 kHz < f < 3.4 kHz
13 18mA IL 45 mA
7 S = closed; R = 7 k, Note 10
RLRTo = 0, VBat = -48V
RLRTo = 2.5 k, VBat = -48V
ILRTo < 23 mA
Min
Typ
Max
Unit
-0.2 0.1 dB
-1.0 0 dB
-2.0 0 dB
-0.2 0.1 dB
-6.22 -6.02 -5.82 dB
-12.24 -12.04 -11.84 dB
-0.2 0.2 dB
-0.1 0.1 dB
-0.2 0.2 dB
-0.1 0.1 dB
-0.2 0.2 dB
12 dBrnC
-78 dBmp
6 dBrnC
-84 dBmp
-67 -50 dB
-67 -50 dB
0.92 IL IL
1.08 IL mA
IL
17
VBat +6
-150
µA
mA
mA
V
Figure 6.
Frequency response, insertion loss,
gain tracking.
1
ωC << RL, RL = 600
R
T
=
60
k,
R
RX
=
60
k
C
TIPX
VTX
RL
VTR ILDC PBL 386 50/2
RT
EL RINGX RSN
RRX
E RX
VTX
5

5 Page





PBL386502SHT arduino
PBL 386 50/2
If calculation of the ZB formula above
yields a balance network containing an
inductor, an alternate method is recom-
mended. Contact Ericsson Microelectron-
ics for assistance.
The PBL 386 50/2 SLIC may also be
used together with programmable
CODEC/filters. The programmable
CODEC/filter allows for system controller
adjustment of hybrid balance to accom-
modate different line impedances without
change of hardware. In addition, the
transmit and receive gain may be
adjusted. Please, refer to the program-
mable CODEC/filter data sheets for
design information.
Longitudinal Impedance
A feed back loop counteracts longitudi-
nal voltages at the two-wire port by
injecting longitudinal currents in opposing
phase.
Thus longitudinal disturbances will
appear as longitudinal currents and the
TIPX and RINGX terminals will experi-
ence very small longitudinal voltage
excursions, leaving metallic voltages well
within the SLIC common mode range.
The SLIC longitudinal impedance per
wire, ZLoT and ZLoR, appears as typically
20to longitudinal disturbances. It
should be noted that longitudinal currents
may exceed the dc loop current without
disturbing the vf transmission.
Capacitors CTC and CRC
The capacitors designated CTC and CRC
in figure 12, connected between TIPX
and ground as well as between RINGX
and ground, can be used for RFI filtering.
The recommended value for CTC and
CRC is 2200 pF. Higher capacitance
values may be used, but care must be
taken to prevent degradation of either
longitudinal balance or return loss. CTC
and CRC contribute to a metallic imped-
ance of 1/(π·f·CTC) = 1/(π·f·CRC), a TIPX to
ground impedance of 1/(2·π·f·CTC) and a
RINGX to ground impedance of
1/(2·π·f·CRC).
VTX
RTX
PBL
386 50/2 ZT ZB
RSN
Z RX
Figure 10. Hybrid function.
AC - DC Separation Capacitor, CHP
The high pass filter capacitor con-
nected between terminals HP and TIPX
provides the separation of the ac signal
from the dc part. CHP positions the low
end frequency response break point of
the ac loop in the SLIC. Refer to table 1
for recommended values of CHP.
Example: A CHP value of 150 nF will
position the low end frequency response
3dB break point of the ac loop at 1.8 Hz
(f3dB) according to f3dB = 1/(2·π·RHP·CHP)
where RHP = 600 k.
High-Pass Transmit Filter
The capacitor CTX in figure 12 con-
nected between the VTX output and the
CODEC/filter forms, together with RTX
and/or the input impedance of a pro-
grammable CODEC/filter, a high-pass
RC filter. It is recommended to position
the 3 dB break point of this filter between
30 and 80 Hz to get a faster response for
the dc steps that may occur at DTMF
signalling.
Capacitor CLP
The capacitor CLP, which connects
between the terminals CLP and VBAT,
positions together with the resistive loop
feed resistor RSG (see section Battery
Feed), the high end frequency break
point of the low pass filter in the dc loop
in the SLIC. CLP together with RSG, CHP
and ZT (see section Two-Wire Imped-
RFB
VT
Combination
CODEC/Filter
VRX
ance) forms the total two wire output
impedance of the SLIC. The choise of
these programmable components have
an influence on the power supply
rejection ratio (PSRR) from VBAT to the
two wire side at sub-audio frequencies.
At these frequencies capacitor CLP also
influences the transversal to longitudinal
balance in the SLIC. Table 1 suggests
suitable values on CLP for different
feeding characteristics. Typical values of
the transversal to longitudinal balance
(T-L bal.) at 200Hz is given in table 1 for
the chosen values on CLP.
RFeed
RSG
CLP T-L bal. CHP
@200Hz
[] [k] [nF] [dB] [nF]
2·50 0
150 -46
47
2·200 60.4 100 -46
150
2·400 147 47 -43
150
2·800 301 22 -36
150
Table 1. RSG , CLP and CHP values for
different feeding characteristics.
11

11 Page







PáginasTotal 16 Páginas
PDF Descargar[ Datasheet PBL386502SHT.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
PBL386502SHTSubscriber Line Interface CircuitEricsson
Ericsson

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar