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Número de pieza PBL386402SOT
Descripción Subscriber Line Interface Circuit
Fabricantes Ericsson 
Logotipo Ericsson Logotipo



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March 2000
PBL 386 40/2
Subscriber Line
Interface Circuit
Description
The PBL 386 40/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated
circuit for use in Digital Loop Carrier, FITL and other telecommunications equipment.
The PBL 386 40/2 has been optimized for low total line interface cost and a high
degree of flexibility in different applications.
The PBL 386 40/2 emulates resistive loop feed, programmable between 2x50
and 2x900 , with short loop current limiting adjustable to max 45 mA. In the current
limited region the loop feed is nearly constant current with a slight slope correspond-
ing to 2x30 k.
A second, lower battery voltage may be connected to the device to reduce short
loop power dissipation. The SLIC automatically switches between the two battery
supply voltages without need for external components or external control.
The SLIC incorporates loop current, ground key and ring trip detection functions.
The PBL 386 40/2 is compatible with both loop and ground start signaling.
Two- to four-wire and four- to two-wire voice frequency (VF) signal conversion is
accomplished by the SLIC in conjunction with either a conventional CODEC/filter or
with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable
two-wire impedance, complex or real, is set by a simple external network.
Longitudinal voltages are suppressed by a feedback loop in the SLIC and the
longitudinal balance specifications meet the DLC requirements.
The PBL 386 40/2 package options are 24-pin SSOP package, 24-pin SOIC and
28-pin PLCC.
DT
DR
TIPX
RINGX
HP
VCC
VBAT2
VBAT
AGND
BGND
Two-wire
Interface
Figure 1. Block diagram.
Ring Trip
Comparator
Ground Key
Detector
Line Feed
Controller
and
Longitudinal
Signal
Suppression
Off-hook
Detector
VF Signal
Transmission
PTG
Ring Relay
Driver
Input
Decoder
and
Control
RRLY
C1
C2
C3
DET
POV
PSG
PLC
LP
PLD
REF
VTX
RSN
Key Features
• 24-pin SSOP package
• High and low battery with automatic
switching
• 65 mW on-hook power dissipation in
active state
• On-hook transmission
• Long loop battery feed tracks Vbat for
maximum line voltage
• Only +5 V feed in addition to battery
• Selectable transmit gain (1x or 0.5x)
• No power-up sequence
• Programmable signal headroom
• 43V open loop voltage @ -48V battery
feed
• Constant loop voltage for line leakage
<5 mA (RLeak ~ >10 k@ -48V)
• Full longitudinal current capability
during on-hook state
• Analog over temperature protection
permits transmission while the
protection circuit is active
• Line voltage measurement
• Polarity reversal
• Ground key detector
• Tip open state with ring ground
detector
• -40°C to +85°C ambient temperature
range
PBL 386 40/2
24-pin SOIC, 24-pin SSOP, 28-pin PLCC
1

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PBL386402SOT pdf
PBL 386 40/2
Parameter
Four-wire to two-wire, g4-2
Four-wire to four-wire, g4-4
Insertion loss
Two-wire to four-wire, G2-4
Four-wire to two-wire, G4-2
Gain tracking
Two-wire to four-wire
Four-wire to two-wire
Noise
Idle channel noise at two-wire
(TIPX-RINGX) or four-wire (VTX) output
Harmonic distortion
Two-wire to four-wire
Four-wire to two-wire
Battery Feed characteristics
Loop current, IL , in the current
limited region, reference A, B & C
Tip open state TIPX current, ILeak
Tip open state RINGX current, ILRTo
Tip open state RINGX voltage, VRTo
Tip voltage (ground start)
Ref
fig Conditions
Min Typ Max
6 relative to 0 dBm, 1.0 kHz. EL=0 V
0.3 kHz < f < 3.4 kHz
-0.2
f = 8 kHz, 12 kHz,
-1.0
16 kHz
-2.0
6 relative to 0 dBm, 1.0 kHz, EL =0 V
0.3 kHz < f < 3.4 kHz
-0.2
0.1
0
0
0.1
6 0 dBm, 1.0 kHz, Note 5
G2-4 = 20 · Log
VTX
VTR
; ERX = 0
PTG = AGND
6 0 dBm, 1.0 kHz, Note 6
G4-2 = 20 · Log
VTR
ERX
; EL = 0
6 Ref. -10 dBm, 1.0 kHz, Note 7
-40 dBm to + 3 dBm
-55 dBm to -40 dBm
6 Ref. -10 dBm, 1.0 kHz,
-40 dBm to + 3 dBm
-55 dBm to -40 dBm
-0.2
-6.22
-0.2
0.2
-6.02 -5.82
0.2
-0.1 0.1
-0.2 0.2
-0.1 0.1
-0.2 0.2
C-message weighting
Psophometrical weighting
Note 8
12
-78
6 0 dBm
0.3 kHz < f < 3.4 kHz
-67 -50
-67 -50
13
18mA IL 45 mA
7 S = closed; R = 7 k, note 10
0.92 IL
IL
1.08 IL
-100
7 RLRTo = 0, VBat = -48V
RLRTo = 2.5 k, VBat = -48V
7 ILRTo < 23 mA
7 Active state, Tip lead open (S open), -4
IL
17
VBat + 6
-2.2
Ring lead to ground through 150
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dBrnC
dBmp
dB
dB
mA
µA
mA
mA
V
V
Figure 6.
Frequency response, insertion loss,
gain tracking.
1 << RL, RL = 600
ωC
RT = 120 k, RRX = 60 k
C
TIPX
VTX
RL
VTR ILDC PBL 386 40/2 RT
EL RINGX RSN
RRX
E RX
VTX
5

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PBL386402SOT arduino
PBL 386 40/2
When choosing RTX, make sure the output
load of the VTX terminal is >20 k.
If calculation of the ZB formula above
yields a balance network containing an
inductor, an alternate method is recom-
mended. Contact Ericsson Microelectron-
ics for assistance.
The PBL 386 40/2 SLIC may also be
used together with programmable
CODEC/filters. The programmable
CODEC/filter allows for system controller
adjustment of hybrid balance to accom-
modate different line impedances without
change of hardware. In addition, the
transmit and receive gain may be ad-
justed. Please, refer to the programm-
able CODEC/filter data sheets for design
information.
VTX
RTX
PBL
386 40/2 ZT ZB
RSN
Z RX
RFB
VT
Combination
CODEC/Filter
VRX
Longitudinal Impedance
A Feed back loop counteracts longitudi-
nal voltages at the two-wire port by
injecting longitudinal currents in opposing
phase.
Thus longitudinal disturbances will
appear as longitudinal currents and the
TIPX and RINGX terminals will experi-
ence very small longitudinal voltage
excursions, leaving metallic voltages well
within the SLIC common mode range.
The SLIC longitudinal impedance per
wire, ZLoT and ZLoR, appears as typically
20 to longitudinal disturbances. It
should be noted that longitudinal currents
may exceed the dc loop current without
disturbing the vf transmission.
Capacitors CTC and CRC
The capacitors designated CTC and CRC
in figure 12, connected between TIPX
and ground as well as between RINGX
and ground, can be used for RFI filter-
ing.. The recommended value for CTC
and CRC is 2200 pF. Higher capacitance
values may be used, but care must be
taken to prevent degradation of either
longitudinal balance or return loss. CTC
and CRC contribute to a metallic imped-
ance of 1/(π·f·CTC) = 1/(π·f·CRC), a TIPX to
ground impedance of 1/(2·π·f·CTC) and a
RINGX to ground impedance of 1/
(2·π·f·CRC).
AC - DC Separation Capacitor, CHP
The high pass filter capacitor connected
between terminals HP and TIPX provides
the separation of the ac signal from the
dc part. CHP positions the low end
Figure 10. Hybrid function.
frequency response break point of the ac
loop in the SLIC. Refer to table 1 for
recommended values of CHP.
Example: A CHP value of 150 nF will
position the low end frequency response
3dB break point of the ac loop at 1.8 Hz
(f3dB) according to f3dB = 1/(2·π·RHP·CHP)
where RHP = 600 k.
High-Pass Transmit Filter
The capacitor CTX in figure 12 connected
between the VTX output and the
CODEC/filter forms, together with RTX
and/or the input impedance of a pro-
grammable CODEC/filter, a high-pass
RC filter. It is recommended to position
the 3 dB break point of this filter between
30 and 80 Hz to get a faster response for
the dc steps that may occur at DTMF
signalling.
Capacitor CLP
The capacitor CLP, which connects between
the terminals CLP and VBAT, positions
together with the resistive loop feed resis-
tor RSG (see section Battery Feed), the high
end frequency break point of the low pass
filter in the dc loop in the SLIC. CLP together
with RSG, CHP and ZT (see section Two-Wire
Impedance) forms the total two wire output
impedance of the SLIC. The choise of
these programmable components have an
influence on the power supply rejection
ratio (PSRR) from VBAT to the two wire
side at sub-audio frequencies. At these
frequencies capacitor CLP also influences
the transversal to longitudinal balance in
the SLIC. Table 1 suggests suitable values
on CLP for different Feeding characteristics.
Typical values of the transversal to longitu-
dinal balance (T-L bal.) at 200Hz is given in
table 1 for the chosen values on CLP.
RFeed RSG CLP T-L bal. CHP
@200Hz
[] [k] [nF] [dB] [nF]
250 0
150 -46
2200 60.4 100 -46
2400 147 47 -43
2800 301 22 -36
47
150
150
150
Table 1. RSG , CLP and CHP values for
different Feeding characteristics.
11

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