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PDF PBL38620-2 Data sheet ( Hoja de datos )

Número de pieza PBL38620-2
Descripción Subscriber Line Interface Circuit
Fabricantes Ericsson 
Logotipo Ericsson Logotipo



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June 1999
PBL 386 20/2
Subscriber Line
Interface Circuit
Description
The PBL 386 20/2 Subscriber Line Interface Circuit (SLIC) is a 90 V bipolar integrated
circuit for use in PBX,Terminal adapters and other telecommunications equipment.
The PBL 386 20/2 has been optimized for low total line interface cost and a high
degree of flexibility in different applications.
The PBL 386 20/2 has constant current feed, programmable to max. 30 mA.
A second lower battery voltage may be connected to the device to reduce short
loop power dissipation. The SLIC automatically switches between the two battery
supply voltages without need for external components or external control.
The SLIC incorporates loop current, ground key and ring trip detection functions.
The PBL 386 20/2 is compatible with loop start signaling.
Two- to four-wire and four- to two-wire voice frequency (VF) signal conversion is
accomplished by the SLIC in conjunction with either a conventional CODEC/filter or
with a programmable CODEC/filter, e.g. SLAC, SiCoFi, Combo II. The programmable
two-wire impedance, complex or real, is set by a simple external network.
Longitudinal voltages are suppressed by a feedback loop in the SLIC and the
longitudinal balance specifications meet Bellcore TR909 requirements.
The PBL 386 20/2 package options are 24-pin SSOP, 24-pin SOIC and 28 pin PLCC.
Key Features
• 24-pin SSOP package
• High and low battery with automatic
switching
• 60 mW on-hook power dissipation in
active state
• On-hook transmission
• Long loop battery feed tracks Vbat for
maximum line voltage
• Only +5 V feed in addition to battery
• Selectable transmit gain (1x or 0.5x)
• No power-up sequence
• 44V open loop voltage @ -48V battery
feed
• Full longitudinal current capability
during on-hook state
• Analog over temperature protection
permits transmission while the
protection circuit is active
• Integrated Ring Relay driver
• Ground key detector
• Programmable signal headroom
DT
DR
TIPX
RINGX
HP
VCC
VBAT2
VBAT
AGND
BGND
Two-wire
Interface
Figure 1. Block diagram.
Ring Trip
Comparator
Ground Key
Detector
Line Feed
Controller
and
Longitudinal
Signal
Suppression
Off-hook
Detector
VF Signal
Transmission
PTG
Ring Relay
Driver
Input
Decoder
and
Control
RRLY
C1
C2
C3
DET
POV
PSG
PLC
LP
PLD
REF
VTX
RSN
PBL 386 20/2
24-pinSOIC, 24-pin SSOP, 28-pin PLCC
1

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PBL38620-2 pdf
PBL 386 20/2
Parameter
Four-wire to two-wire, g4-2
Four-wire to four-wire, g
4-4
Insertion loss
Two-wire to four-wire, G2-4
Four-wire to two-wire, G4-2
Gain tracking
Two-wire to four-wire
Four-wire to two-wire
Noise
Idle channel noise at two-wire
(TIPX-RINGX) or four-wire (VTX) output
Harmonic distortion
Two-wire to four-wire
Four-wire to two-wire
Battery feed characteristics
Constant loop current, I
LProg
ILProg @ 30 mA
ILProg @ 18 mA
Open circuit state loop current, I LOC
Ref
fig Conditions
6 relative to 0 dBm, 1.0 kHz. EL=0 V
0.3 kHz < f < 3.4 kHz
f = 8 kHz, 12 kHz,
16 kHz
6 relative to 0 dBm.1.0 kHz, E =0 V
L
0.3 kHz < f < 3.4 kHz
6 0 dBm, 1.0 kHz, Note 5
G2-4 = 20 · Log
VTX
VTR
; ERX = 0
PTG = AGND
6 0 dBm, 1.0 kHz, Note 6
G4-2 = 20 · Log
VTR
ERX
; EL = 0
6 Ref. -10 dBm, 1.0 kHz, Note 7
-40 dBm to + 0 dBm
-55 dBm to -40 dBm
6 Ref. -10 dBm
-40 dBm to + 0 dBm
-55 dBm to -40 dBm
C-message weighting
Psophometrical weighting
Note 8
6 0 dBm
0.3 kHz < f < 3.4 kHz
12 I = 1 000 - 4.0 (mA)
LProg
RLC
12
ILProg
=
1 000
RLC
- 4.2 (mA)
12
ILProg
=
1 000
RLC
- 3.9 (mA)
RLC in k
RL = 0
Min Typ
-0.2
-1.0
-2.0
-0.2
-0.2
-6.22
-6.02
-0.2
-0.1
-0.2
-0.1
-0.2
-67
-67
0.92 I I
LProg LProg
0.95 ILProg ILProg
0.94 ILProg ILProg
-100
0
Max
Unit
0.1 dB
0 dB
0 dB
0.1 dB
0.2
-5.82
dB
dB
0.2 dB
0.1 dB
0.2 dB
0.1 dB
0.2 dB
12 dBrnC
-78 dBmp
-50 dB
-50 dB
1.08 I mA
LProg
1.05 ILProg mA
1.06 ILProg mA
100 µA
Figure 6.
Frequency response, insertion loss,
gain tracking.
1 << RL, RL = 600
ωC
RT = 120 k, RRX = 60 k
C
TIPX
VTX
RL
VTR ILDC PBL 386 20/2
RT
EL RINGX RSN
RRX
E RX
VTX
5

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PBL38620-2 arduino
PBL 386 20/2
hybrid balance to accommodate different
line impedances without change of
hardware. In addition, the transmit and
receive gain may be adjusted. Please, refer
to the programmable CODEC/filter data
sheets for design information.
Longitudinal Impedance
A feed back loop counteracts longitudinal
voltages at the two-wire port by injecting
longitudinal currents in opposing phase.
Thus longitudinal disturbances will
appear as longitudinal currents and the
TIPX and RINGX terminals will experience
very small longitudinal voltage excursions,
leaving metallic voltages well within the
SLIC common mode range.
The SLIC longitudinal impedance per
wire, ZLoT and ZLoR, appears as typically
20to longitudinal disturbances. It should
be noted that longitudinal currents may
exceed the dc loop current without distur-
bing the vf transmission.
Capacitors CTC and CRC
The capacitors designated CTC and CRC
in figure 12, connected between TIPX
and ground as well as between RINGX
and ground, can be used for RFI filtering.
The recommended value for CTC and
CRC is 2200 pF. Higher capacitance
values may be used, but care must be
taken to prevent degradation of either
longitudinal balance or return loss. CTC
and CRC contribute to a metallic imped-
ance of 1/(π·f·CTC) = 1/(π·f·CRC), a TIPX to
ground impedance of1/(2·π·f·CTC) and a
RINGX to ground impedance of
1/(2·π·f·CRC).
AC - DC Separation Capacitor, CHP
The high pass filter capacitor connected
between terminals HP and TIPX provides
the separation of the ac signal from the
dc part. CHP positions the low end
frequency response break point of the ac
loop in the SLIC. Refer to table 1 for a
recommended value of CHP.
Example: A CHP value of 47 nF will
position the low end frequency response
3dB break point of the ac loop at 5.6 Hz
(f3dB) according to f3dB = 1/(2⋅π⋅RHPCHP)
where RHP = 600k .
High-Pass Transmit Filter
The capacitor CTX in figure 12 connected
between the VTX output and the
CODEC/filter forms, together with RTX and/
or the input impedance of a programmable
CODEC/filter, a high-pass RC filter. It is
RFB
VTX
RTX
PBL
386 20/2 ZT ZB
RSN
Z RX
VT
Combination
CODEC/Filter
VRX
Figure 10. Hybrid function.
recommended to position the 3 dB break
point of this filter between 30 and 80 Hz to
get a faster response for the dc steps that
may occur at DTMF signalling.
Capacitor CLP
The capacitor CLP, which connects between
the terminals CLP and VBAT, positions the
high end frequency break point of the low
pass filter in the dc loop in the SLIC. CLP
together with CHP and ZT (see section Two-
Wire Impedance) forms the total two wire
output impedance of the SLIC. The choise
of these programmable components have
an influence on the power supply rejection
ratio (PSRR) from VBAT to the two wire
side at sub-audio frequencies. At these
frequencies capacitor CLP also influences
the transversal to longitudinal balance in
the SLIC. Table 1 suggests a suitable value
on CLP. The typical value of the transversal
to longitudinal balance (T-L bal.) at 200Hz
is given in table 1 for the chosen value on
CLP.
Battery Feed
The PBL 386 20/2 SLIC emulate a battery
characteristic with current limitation
adjustable.The open loop voltage measured
between the TIPX and RINGX terminals is
tracking the battery voltage VBat. The
signalling headroom, or overhead voltage
VTRO, is programmable with a resistor ROV
connected between terminal POV on the
SLIC and ground. Please refer to section
“Programmable overhead voltage(POV)”.
The battery voltage overhead,VOH,depends
on the programmed signal overhead voltage
VTRO . VOH defines the TIP to RING voltage
at open loop conditions according to
VTR(at IL = 0 mA) = |VBat| - VOH.
Refer to table 2 for the typical value on
VOH.
SLIC
VOH(typ) [V]
PBL 386 20/2
2.5 +VTRO
Table 2. Battery overhead.
RFeed
[]
2·25
T-L bal.
RSG CLP @ 200Hz CHP
[k] [nF] [dB] [nF]
0 150 -46 47
Table 1. RSG, CLP and CHP values for cons-
tant current feeding characteristics.
For values outside table 1, please contact
Ericsson Microelectronics for assistance.
The current limit (reference A - C in figure
13) is adjusted by connecting a resistor,
RLC, between terminal PLC and ground
according to the equation:
RLC =
1000
ILProg + 4
where RLC is in kfor ILProg in mA.
A second, lower battery voltage may be
connected to the device at terminal VBAT2
to reduce short loop power dissipation.
The SLIC automatically switches between
the two battery supply voltages without need
for external control. The silent battery
11

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