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PDF PALLV22V10Z-25PI Data sheet ( Hoja de datos )

Número de pieza PALLV22V10Z-25PI
Descripción Low-Voltage Zero Power 24-Pin EE CMOS Versatile PAL Device
Fabricantes Lattice Semiconductor 
Logotipo Lattice Semiconductor Logotipo



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No Preview Available ! PALLV22V10Z-25PI Hoja de datos, Descripción, Manual

PALLV22V10 COM'L: -7/10/15
PALLV22V10Z
IND: -15
IND: -25
PALLV22V10 and PALLV22V10Z Families
Low-Voltage (Zero Power) 24-Pin EE CMOS
Versatile PAL Device
DISTINCTIVE CHARACTERISTICS
x Low-voltage operation, 3.3 V JEDEC compatible
— VCC = + 3.0 V to 3.6 V
x Commercial and industrial operating temperature range
x 7.5-ns tPD
x Electrically-erasable technology provides reconfigurable logic and full testability
x 10 macrocells programmable as registered or combinatorial, and active high or active low to
match application needs
x Varied product term distribution allows up to 16 product terms per output for complex
functions
x Global asynchronous reset and synchronous preset for initialization
x Power-up reset for initialization and register preload for testability
x Extensive third-party software and programmer support
x 24-pin SKINNY DIP and 28-pin PLCC packages save space
GENERAL DESCRIPTION
The PALLV22V10 is an advanced PAL® device built with low-voltage, high-speed, electrically-
erasable CMOS technology.
The PALLV22V10Z provides low voltage and zero standby power. At 30 µA maximum standby
current, the PALLV22V10Z allows battery powered operation for an extended period.
The PALLV22V10 device implements the familiar Boolean logic transfer function, the sum of
products. The PAL device is a programmable AND array driving a fixed OR array. The AND array
is programmed to create custom product terms, while the OR array sums selected terms at the
outputs.
The product terms are connected to the fixed OR array with a varied distribution from 8 to 16
across the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell.
Each macrocell can be programmed as registered or combinatorial, and active high or active low.
The output configuration is determined by two bits controlling two multiplexers in each macrocell.
Publication# 18956 Rev: F
Amendment/0
Issue Date: September 2000

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PALLV22V10Z-25PI pdf
Note that preset and reset control the flip-flop, not the output pin. The output level is determined
by the output polarity selected.
Benefits of Lower Operating Voltage
The PALLV22V10 has an operating voltage range of 3.0 V to 3.6 V. Low voltage allows for lower
operating power consumption, longer battery life, and/or smaller batteries for notebook
applications.
Because power is proportional to the square of the voltage, reduction of the supply voltage from
5.0 V to 3.3 V significantly reduces power consumption. This directly translates to longer battery
life for portable applications. Lower power consumption can also be used to reduce the size and
weight of the battery. Thus, 3.3 V designs facilitate a reduction in the form factor.
A lower operating voltage results in a reduction of I/O voltage swings. This reduces noise
generation and provides a less hostile environment for board design. A lower operating voltage
also reduces electromagnetic radiation noise and makes obtaining FCC approval easier.
3.3-V (CMOS) and 5-V (CMOS and TTL) Compatible Inputs and I/O
Input voltages can be at TTL levels. Additionally, the PALLV22V10 can be driven with true 5-V
CMOS levels due to special input and I/O buffer circuitry.
Power-Up Reset
All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the
PALLV22V10 will depend on the programmed output polarity. The VCC rise must be monotonic,
and the reset delay time is 1000ns maximum.
Register Preload
The registers on the PALLV22V10 can be preloaded from the output pins to facilitate functional
testing of complex state machine designs. This feature allows direct loading of arbitrary states,
making it unnecessary to cycle through long test vector sequences to reach a desired state. In
addition, transitions from illegal states can be verified by loading illegal states and observing
proper recovery.
Security Bit
After programming and verification, a PALLV22V10 design can be secured by programming the
security EE bit. Once programmed, this bit defeats readback of the internal programmed pattern
by a device programmer, securing proprietary designs from competitors. When the security bit is
programmed, the array will read as if every bit is erased, and preload will be disabled.
The bit can only be erased in conjunction with erasure of the entire pattern.
Programming and Erasing
The PALLV22V10 can be programmed on standard logic programmers. It also may be erased to
reset a previously configured device back to its unprogrammed state. Erasure is automatically
performed by the programming hardware. No special erase operation is required.
PALLV22V10 and PALLV22V10Z Families
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PALLV22V10Z-25PI arduino
CAPACITANCE 1
Parameter
Symbol
CIN
COUT
Parameter Description
Input Capacitance
Output Capacitance
VIN = 2.0 V
VOUT = 2.0 V
Test Condition
VCC = 3.3 V
TA = 25°C
f = 1 MHz
Typ
5
8
Unit
pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
SWITCHING CHARACTERISTICS OVER INDUSTRIAL OPERATING RANGES 1
Parameter
Symbol
tPD
tS
tH
tCO
tAR
tARW
tARR
tSPR
tWL
tWH
fMAX
tEA
tER
Parameter Description
Input or Feedback to Combinatorial Output (Note 2)
Setup Time from Input, Feedback or SP to Clock
Hold Time
Clock to Output
Asynchronous Reset to Registered Output
Asynchronous Reset Width
Asynchronous Reset Recovery Time
Synchronous Preset Recovery Time
Clock Width
LOW
HIGH
External Feedback
Maximum Frequency (Note 3)
Internal Feedback (fCNT)
No Feedback
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
1/(tS + tCO)
1/(tS + tCF) (Note 4)
1/(tWH + tWL)
-25
Min Max
25
15
0
15
25
25
25
25
10
10
33.3
35.7
50
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
Notes:
1. See “Switching Test Circuit” for test conditions.
2. This parameter is tested in Standby Mode. When the device is not in Standby Mode, the tPD may be slightly faster.
3. These parameters are not 100% tested, but are evaluated at initial characterization and at any time
the design is modified where frequency may be affected.
4. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) - tS.
PALLV22V10Z-25
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