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PDF PALLV16V8Z-20PI Data sheet ( Hoja de datos )

Número de pieza PALLV16V8Z-20PI
Descripción Low Voltage/ Zero Power 20-Pin EE CMOS Universal Programmable Array Logic
Fabricantes Lattice Semiconductor 
Logotipo Lattice Semiconductor Logotipo



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No Preview Available ! PALLV16V8Z-20PI Hoja de datos, Descripción, Manual

FINAL
COM’L:-10
IND:-20
PALLV16V8-10 and PALLV16V8Z-20
Low Voltage, Zero Power 20-Pin EE CMOS
Universal Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
x Low-voltage operation, 3.3 V JEDEC compatible
— VCC = +3.0 V to +3.6 V
x Pin and function compatible with all 20-pin PAL® devices
x Electrically-erasable CMOS technology provides reconfigurable logic and full testability
x Direct plug-in replacement for the PAL16R8 series
x Designed to interface with both 3.3-V and 5-V logic
x Outputs programmable as registered or combinatorial in any combination
x Programmable output polarity
x Programmable enable/disable control
x Preloadable output registers for testability
x Automatic register reset on power up
x Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages
x Extensive third-party software and programmer support
x Fully tested for 100% programming and functional yields and high reliability
GENERAL DESCRIPTION
The PALLV16V8 is an advanced PAL device built with low-voltage, high-speed, electrically-erasable
CMOS technology. It is functionally compatible with all 20-pin GAL devices. The macrocells
provide a universal device architecture. The PALLV16V8 will directly replace the PAL16R8, with the
exception of the PAL16C1.
The PALLV16V8Z provides zero standby power and high speed. At 30-µA maximum standby
current, the PALLV16V8Z allows battery powered operation for an extended period.
The PALLV16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to
implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic can
always be reduced to sum-of-products form, taking advantage of the very wide input gates
available in PAL devices. The equations are programmed into the device through floating-gate cells
in the AND logic array that can be erased electrically.
The fixed OR array allows up to eight data product terms per output for logic functions. The sum
of these products feeds the output macrocell. Each macrocell can be programmed as registered or
combinatorial with an active-high or active-low output. The output configuration is determined by
two global bits and one local bit controlling four multiplexers in each macrocell.
Publication# 17713 Rev: E
Amendment/0
Issue Date: November 1998

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PALLV16V8Z-20PI pdf
Table 1. Macrocell Configuration
Cell
SG0 SG1 SL0X Configuration
Devices
Emulated
Device Uses Registers
Cell
SG0 SG1 SL0X Configuration
Devices
Emulated
Device Uses No Registers
010
Registered
Output
PAL16R8, 16R6,
16R4
1
0
0
Combinatorial
Output
PAL10H8, 12H6,
14H4, 16H2, 10L8, 12L6,
14L4, 16L2
0
1
1
Combinatorial
I/O
PAL16R6, 16R4
1
0
1
Input
PAL12H6, 14H4, 16H2, 12L6,
14L4, 16L2
1
1
1
Combinatorial
I/O
PAL16L8
Programmable Output Polarity
The polarity of each macrocell can be active-high or active-low, either to match output signal
needs or to reduce product terms. Programmable polarity allows Boolean expressions to be written
in their most compact form (true or inverted), and the output can still be of the desired polarity.
It can also save “DeMorganizing” efforts.
Selection is through a programmable bit SL1x which controls an exclusive-OR gate at the output
of the AND/OR logic. The output is active high if SL1x is 1 and active low if SL1x is 0.
PALLV16V8-10 and PALLV16V8Z-20 Families
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PALLV16V8Z-20PI arduino
ABSOLUTE MAXIMUM RATINGS
Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature
with Power Applied . . . . . . . . . . . . . .-55°C to +125°C
Supply Voltage with
Respect to Ground . . . . . . . . . . . . . . . -0.5 V to +7.0 V
DC Input Voltage . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V
DC Output or I/O
Pin Voltage . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V
Static Discharge Voltage . . . . . . . . . . . . . . . . . 2001 V
Latch-up Current
(TA = 0°C to 75°C) . . . . . . . . . . . . . . . . . . . . . 100 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Programming conditions may differ.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA)
Operating in Free Air . . . . . . . . . . . . . . . 0°C to +75°C
Supply Voltage (VCC)
with Respect to Ground . . . . . . . . . . . +3.0 V to +3.6 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES
Parameter
Symbol
Parameter Description
Test Conditions
Min Max Unit
VOH Output HIGH Voltage
VIN = VIH or VIL
VCC = Min
IOH = –2 mA
IOH = –75 mA
2.4
VCC - 0.2 V
V
V
VOL Output LOW Voltage
VIN = VIH or VIL
VCC = Min
IOL = 2 mA
IOL = 100 mA
0.4 V
0.2 V
VIH Input HIGH Voltage
Guaranteed Input Logical HIGH Voltage for all Inputs (Note 1)
2.0
5.5 V
VIL Input LOW Voltage
Guaranteed Input Logical LOW Voltage for all Inputs (Note 1)
0.8 V
IIH
Input HIGH Leakage Current
VIN = VCC, VCC = Max (Note 2)
10 µA
IIL
Input LOW Leakage Current
VIN = 0 V, VCC = Max (Note 2)
–100 µA
IOZH Off-State Output Leakage Current HIGH VOUT = VCC, VCC = Max, VIN = VIH or VIL (Note 2)
10 µA
IOZL Off-State Output Leakage Current LOW VOUT = VCC, VCC = Max, VIN = VIH or VIL (Note 2)
-100 µA
ISC
Output Short-Circuit Current
VOUT = 0.5 V, VCC = Max (Note 3)
-50 -130 mA
ICC Supply Current
Outputs Open (IOUT = 0 mA), VCC = Max, f = 15 MHz (Note 4)
55 mA
Notes:
1. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included.
2. I/O pin leakage is the worst case of IIL and IOZL (or IIL and IOZL).
3. Not more than one output should be shortened at a time, and the duration of the short-circuit should not exceed one second.
VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation.
4. This parameter is guaranteed worst case under test conditions. Refer to the ICC vs. frequency graph for typical measurements.
PALLV16V8-10 (Com’l)
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