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Número de pieza PALCE29MA16H-25JC
Descripción 24-Pin EE CMOS Programmable Array Logic
Fabricantes Advanced Micro Devices 
Logotipo Advanced Micro Devices Logotipo



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FINAL
COM’L: H-25
PALCE29MA16H-25
24-Pin EE CMOS Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
s High-performance semicustom logic
replacement; Electrically Erasable (EE)
technology allows reprogrammability
s 16 bidirectional user-programmable I/O logic
macrocells for Combinatorial/Registered/
Latched operation
s Output Enable controlled by a pin or product
terms
s Varied product term distribution for increased
design flexibility
s Programmable clock selection with common
pin clock/latch enable (LE) or individual
product term clock/LE with LOW/HIGH clock/
LE polarity
GENERAL DESCRIPTION
The PALCE29MA16 is a high-speed, EE CMOS Pro-
grammable Array Logic (PAL) device designed for gen-
eral logic replacement in TTL or CMOS digital systems.
It offers high speed, low power consumption, high
BLOCK DIAGRAM
s Register/Latch Preload permits full logic
verification
s High speed (tPD = 25 ns, fMAX = 33 MHz and fMAX
internal = 50 MHz)
s Full-function AC and DC testing at the factory
for high programming and functional yields
and high reliability
s 24-pin 300 mil SKINNYDIP and 28-pin plastic
leaded chip carrier packages
s Extensive third-party software and programmer
support through FusionPLD partners
programming yield, fast programming, and excellent
reliability. PAL devices combine the flexibility of custom
logic with the off-the-shelf availability of standard
products, providing major advantages over other
CLK/LE
I/OF7
I/OF6
I/O7
I/O6
I/O 5
I/O 4
I/OF5
I/OF4
I/O
Logic
Macrocell
4
4
I/O
Logic
Macrocell
4
4
I/O
Logic
Macrocell
4
8
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
4
12
4
12
4
8
4
4
4
4
Programmable
AND Array
58x178
4
4
4
4
8
4
12
4
12
4
8
4
4
4
4
4
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
I/O
Logic
Macrocell
4
I 0 -I3 I/OE
I/OF0
I/OF1
I/O0
I/O1
I/O2
I/O3
I/OF2
I/OF3
08811G-1
Publication# 08811 Rev. G Amendment /0
Issue Date: June 1993
2-349

1 page




PALCE29MA16H-25JC pdf
The output polarity for each macrocell in each of the
three modes of operation is user-selectable, allowing
complete flexibility of the macrocell configuration.
Eight of the macrocells (I/OF0–I/OF7) have two inde-
pendent feedback paths to the AND array (see Figure
2b). The first is a dedicated I/O pin feedback to the AND
array for combinatorial input. The second path consists
of a direct register/latch feedback to the array. If the pin
is used as a dedicated input using the first feedback
path, the register/latch feedback path is still available to
the AND array. This path provides the capability of using
the register/latch as a buried state register/latch. The
other eight macrocells have a single feedback path to
the AND array. This feedback is user-selectable as
either an I/O pin or a register/latch feedback (see
Figure 2a).
Each macrocell can provide true input/output capability.
The user can select each macrocell register/latch to be
driven by either the signal generated by the AND-OR ar-
ray or the corresponding I/O pin. When the I/O pin is se-
lected as the input, the feedback path provides the
register/latch input to the array. When used as an input,
each macrocell is also user-programmable for regis-
tered, latched, or combinatorial input.
The PALCE29MA16 has a dedicated CLK/LE pin and
one individual CLK/LE product term or macrocell. All
macrocells have a programmable switch to choose be-
tween the CLK/LE pin and the CLK/LE product term as
the clock or latch enable signal. These signals are clock
signals for macrocells configured as registers and latch
enable signals for macrocells configured as latches.
The polarity of these CLK/LE signals is also individually
programmable. Thus different registers or latches can
be driven by different clocks and clock phases.
The Output-Enable mode of each of the macrocells can
be selected by the user. The I/O pin can be configured
as an output pin (permanently enabled) or as an input
pin (permanently disabled). It can also be configured as
AMD
a dynamic I/O controlled by the Output Enable pin or by
a product term.
I/O Logic Macrocell Configuration
AMD’s unique I/O macrocell offers major benefits
through its versatile, programmable input/output cell
structure, multiple clock choices, flexible Output Enable
and feedback selection. Eight I/O macrocells with single
feedback contain 9 EE cells, while the other eight ma-
crocells contain 8 EE cells for programming the input/
output functions (see Table 1).
EE cell S1 controls whether the macrocell will be combi-
natorial or registered/latched. S0 controls the output po-
larity (active-HIGH or active-LOW). S2 determines
whether the storage element is a register or a latch. S3
allows the use of the macrocell as an input register/latch
or as an output register/latch. It selects the direction of
the data path through the register/latch. If connected to
the usual AND-OR array output, the register/latch is an
output connected to the I/O pin. If connected to the I/O
pin, the register/latch becomes an input register/latch to
the AND array using the feedback data path.
Programmable EE cells S4 and S5 allow the user to se-
lect one of the four CLK/LE signals for each macrocell.
S6 and S7 are used to control Output Enable as pin con-
trolled, product-term controlled, permanently enabled or
permanently disabled. S8 controls a feedback multi-
plexer for the macrocells with a single feedback path
only.
Using the programmable EE cells S0–S8 various input
and output configurations can be selected. Some of the
possible configuration options are shown in Figure 3.
In the erased state (charged, disconnected), an archi-
tectural cell is said to have a value of “1”; in the pro-
grammed state (discharged, connected to GND), an
architectural cell is said to have a value of “0.”
Common I/OE (Pin)
Individual OE
Individual Asynchronous Preset
P0
P3
Common CLK/LE (PIN)
Individual CLK/LE
11
10
01
00
S4 S5
Preset
1
0
DQ
Q
S3
CLK/LE
Reset
S2
VCC
11
01
10
00
01
11
10
00
S6 S7
S0 S1
I/OFX
Individual Asynchronous Reset
To AND Array
To AND Array
RFX
Figure 2b. PALCE29MA16 Macrocell (Dual Feedback)
PALCE29MA16H-25
08811G-5
2-353

5 Page





PALCE29MA16H-25JC arduino
LOGIC DIAGRAM
SKINNY DIP (PLCC) Pinouts
Continued from Previous Page
0
4
8 12 16 20 24 28 32
36 40
44 48
52 56
(9) 7
I/O 2
Input/
Output
Macro
AMD
Input/
Output
Macro
18 (21)
I/O 5
(10) 8
I/O3
Input/
Output
Macro
(11) 9
I/OF2
Input/
Output
Macro
(12) 10
I/OF 3
Input/
Output
Macro
PRELOAD
PRODUCT
TERM
(13) 11
I/OE
0
4
8 12 16 20 24 28 32
36 40
44 48
52 56
PALCE29MA16H-25
Input/
Output
Macro
17 (20)
I/O4
Input/
Output
Macro
16 (19)
I/OF5
Input/
Output
Macro
15 (18)
I/OF4
14 (17)
I2
13 (16)
I1
08811G-19
(concluded)
2-359

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