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PDF RF1S30N06LESM Data sheet ( Hoja de datos )

Número de pieza RF1S30N06LESM
Descripción 30A/ 60V/ ESD Rated/ 0.047 Ohm/ Logic Level N-Channel Power MOSFETs
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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Data Sheet
RFP30N06LE, RF1S30N06LESM
April 1999 File Number 3629.2
[ /Title
(RFP3
0N06L
E,
RF1S3
0N06L
ESM)
/Sub-
ject
(30A,
60V,
ESD
Rated,
0.047
Ohm,
Logic
Level
N-
Chan-
nel
Power
MOS-
FETs)
/Autho
r ()
/Key-
words
(Inter-
sil
Corpo-
ration,
ESD
Rated,
0.047
Ohm,
Logic
Level
N-
Chan-
30A, 60V, ESD Rated, 0.047 Ohm, Logic
Level N-Channel Power MOSFETs
These are N-Channel power MOSFETs manufactured using
the MegaFET process. This process, which uses feature
sizes approaching those of LSI integrated circuits gives
optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers and relay drivers. These transistors can be operated
directly from integrated circuits.
These transistors incorporate ESD protection and are
designed to withstand 2kV (Human Body Model) of ESD.
Formerly developmental type TA49027.
Ordering Information
PART NUMBER
PACKAGE
BRAND
RFP30N06LE
TO-220AB
F30N06LE
RF1S30N06LESM TO-263AB
1S30N06L
NOTE: When ordering use the entire part number. Add suffix, 9A, to
obtain the TO-263 variant in tape and reel i.e. RF1S30N06LESM9A.
Packaging
JEDEC TO-220AB
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
Features
• 30A, 60V
• rDS(ON) = 0.047
• 2kV ESD Protected
• Temperature Compensating PSPICE™ Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
JEDEC TO-263AB
GATE
SOURCE
DRAIN
(FLANGE)
6-260
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE™ is a trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999

1 page




RF1S30N06LESM pdf
RFP30N06LE, RF1S30N06LESM
Typical Performance Curves Unless Otherwise Specified (Continued)
2000
1500
1000
500
0
0
CISS
COSS
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS CDS + CGD
CRSS
5
10 15
20
VDS, DRAIN TO SOURCE VOLTAGE (V)
25
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
60
VDD = BVDSS
45
VDD = BVDSS
5.0
3.75
30 2.5
0.75 BVDSS 0.75 BVDSS
0.50 BVDSS 0.50 BVDSS
15
0.25 BVDSS 0.25 BVDSS
RL = 2.0
1.25
IG(REF) = 0.62mA
VGS = 5V
00
IG(REF)
20
IG(ACT)
t, TIME (s)
IG(REF)
80
IG(ACT)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
RG
tP
0V
L
DUT
+
VDD
-
IAS
0.01
0
tP
IAS
BVDSS
VDS
VDD
tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
VGS
0V
VGS
RGS
RL
VDS
+
-
DUT
FIGURE 16. SWITCHING TIME TEST CIRCUIT
6-264
VDS
tON
td(ON)
tr
90%
tOFF
td(OFF)
tf
90%
10%
0
VGS
10%
0
50%
PULSE WIDTH
10%
90%
50%
FIGURE 17. RESISTIVE SWITCHING WAVEFORMS

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