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PDF RF1K49156 Data sheet ( Hoja de datos )
| Número de pieza | RF1K49156 | |
| Descripción | 6.3A/ 30V/ 0.030 Ohm/ Logic Level/ Single N-Channel LittleFET Power MOSFET | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Data Sheet
RF1K49156
August 1999 File Number 4011.3
6.3A, 30V, 0.030 Ohm, Logic Level, Single
N-Channel LittleFET™ Power MOSFET
This Single N-Channel power MOSFET is manufactured
using an advanced MegaFET process. This process, which
uses feature sizes approaching those of LSI integrated
circuits, gives optimum utilization of silicon, resulting in
outstanding performance. It was designed for use in
applications such as switching regulators, switching
converters, motor drivers, relay drivers, and low voltage bus
switches. This product achieves full rated conduction at a
gate bias in the 3V - 5V range, thereby facilitating true on-off
power control directly from logic level (5V) integrated circuits.
Formerly developmental type TA49156.
Ordering Information
PART NUMBER
PACKAGE
BRAND
RF1K49156
MS-012AA
RF1K49156
NOTE: When ordering, use the entire part number. For ordering in tape
and reel, add the suffix 96 to the part number, i.e., RF1K4915696.
Features
• 6.3A, 30V
• rDS(ON) = 0.030Ω
• Temperature Compensating PSPICE® Model
• On-Resistance vs Gate Drive Voltage Curves
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
NC (1)
DRAIN (8)
SOURCE (2)
DRAIN (7)
SOURCE (3)
GATE (4)
DRAIN (6)
DRAIN (5)
Packaging
JEDEC MS-012AA
BRANDING DASH
1
2
3
4
5
8-115
CAUTION: These devices are sensitive to electrostatic discharge; follow properS ESD Handling Procedures.
LittleFET™ is a trademark of Intersil Corporation. PSPICE™ is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1 page  
RF1K49156
Typical Performance Curves (Continued)
2.0
VGS = VDS, ID = 250µA
1.5
2.0
ID = 250µA
1.5
1.0 1.0
0.5 0.5
0
-80 -40
0
40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
2500
2000
1500
1000
CISS
COSS
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS = CDS + CGD
500
0
0
CRSS
5 10 15 20
VDS, DRAIN TO SOURCE VOLTAGE (V)
25
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
VDS
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
tP
0V
RG
L
DUT
+
VDD
-
IAS
0.01Ω
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
0
-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
30 5.00
22.5
VDD = BVDSS
VDD = BVDSS
3.75
15
RL = 4.76Ω
IG(REF) = 0.65mA
VGS = 5V
2.50
PLATEAU VOLTAGES IN
DESCENDING ORDER:
7.5 VDD = BVDSS
VDD = 0.75 BVDSS
VDD = 0.50 BVDSS
VDD = 0.25 BVDSS
1.25
00
20 I-I-G-G-----((--AR-----CE----F-T---)-)
t, TIME (µs)
80 I-I-G-G-----((--AR-----CE----F-T---)-)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
tP
IAS
BVDSS
VDS
VDD
0
tAV
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
8-119
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet RF1K49156.PDF ] | |
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