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PDF RF1K49086 Data sheet ( Hoja de datos )

Número de pieza RF1K49086
Descripción 3.5A/ 30V/ 0.06 Ohm/ Dual N-Channel LittleFET Power MOSFET
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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Data Sheet
RF1K49086
August 1999 File Number 3986.5
3.5A, 30V, 0.06 Ohm, Dual N-Channel
LittleFET™ Power MOSFET
This Dual N-Channel power MOSFET is manufactured using
an advanced MegaFET process. This process, which uses
feature sizes approaching those of LSI integrated circuits,
gives optimum utilization of silicon, resulting in outstanding
performance. It is designed for use in applications such as
switching regulators, switching convertors, motor drivers,
relay drivers, and low voltage bus switches. This device can
be operated directly from integrated circuits.
Formerly developmental type TA49086.
Ordering Information
PART NUMBER
PACKAGE
BRAND
RF1K49086
MS-012AA
RF1K49086
NOTE: When ordering, use the entire part number. For ordering in
tape and reel, add the suffix 96 to the part number, i.e., RF1K4908696.
Features
• 3.5A, 30V
• rDS(ON) = 0.060
• Temperature Compensating PSPICE® Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D1(8)
D1(7)
S1(1)
G1(2)
D2(6)
D2(5)
S2(3)
G2(4)
Packaging
JEDEC MS-012AA
BRANDING DASH
1
2
3
4
5
8-87
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
LittleFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999

1 page




RF1K49086 pdf
RF1K49086
Typical Performance Curves (Continued)
2.0
ID = 250µA
1.5
1.0
0.5
0.0
-80
-40 0 40 80 120
TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
100 0
750
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS = CDS + CGD
CISS
500
COSS
250
CRSS
00 5 10 15 20 25
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
30 10.0
22.5
VDD = BVDSS
VDD = BVDSS
7.5
RL = 8.57
15
IG(REF) = 0.75mA
VGS = 10V
5.0
PLATEAU VOLTAGES IN
DESCENDING ORDER:
7.5 VDD = BVDSS
2.5
VDD = 0.75 BVDSS
VDD = 0.50 BVDSS
VDD = 0.25 BVDSS
00
20 I-I-GG-----((--AR----CE----FT----)) t, TIME (µs)
80 I-I-GG-----((--AR----CE----FT----))
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 14. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
tP
0V
RG
L
DUT
+
VDD
-
IAS
0.01
0
tP
IAS
BVDSS
VDS
VDD
tAV
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
8-91

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