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PDF PALCE20V8 Data sheet ( Hoja de datos )
| Número de pieza | PALCE20V8 | |
| Descripción | EE CMOS 24-Pin Universal Programmable Array Logic | |
| Fabricantes | Lattice Semiconductor | |
| Logotipo |  |
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COM'L: H-5/7/10/15/25, Q-10/15/25 IND: H-15/25, Q-20/25
PALCE20V8 Family
EE CMOS 24-Pin Universal
Programmable Array Logic
DISTINCTIVE CHARACTERISTICS
x Pin and function compatible with all PAL® 20V8 devices
x Electrically erasable CMOS technology provides reconfigurable logic and full testability
x High-speed CMOS technology
— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version
x Direct plug-in replacement for a wide range of 24-pin PAL devices
x Programmable enable/disable control
x Outputs individually programmable as registered or combinatorial
x Peripheral Component Interconnect (PCI) compliant
x Preloadable output registers for testability
x Automatic register reset on power-up
x Cost-effective 24-pin plastic SKINNY DIP and 28-pin PLCC packages
x Extensive third-party software and programmer support
x Fully tested for 100% programming and functional yields and high reliability
x Programmable output polarity
x 5-ns version utilizes a split leadframe for improved performance
GENERAL DESCRIPTION
The PALCE20V8 is an advanced PAL device built with low-power, high-speed, electrically-
erasable CMOS technology. Its macrocells provide a universal device architecture. The
PALCE20V8 is fully compatible with the GAL20V8 and can directly replace PAL20R8 series
devices and most 24-pin combinatorial PAL devices.
Device logic is automatically configured according to the user’s design specification. A design is
implemented using any of a number of popular design software packages, allowing automatic
creation of a programming file based on Boolean or state equations. Design software also verifies
the design and can provide test vectors for the finished device. Programming can be
accomplished on standard PAL device programmers.
The PALCE20V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to
implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic
can always be reduced to sum-of-products form, taking advantage of the very wide input gates
available in PAL devices. The equations are programmed into the device through floating-gate
cells in the AND logic array that can be erased electrically.
Publication# 16491 Rev: E
Amendment/0
Issue Date: November 1998
1 page  
Dedicated Input in a Non-Registered Device
The control bit settings are SG0 = 1, SG1 = 0 and SL0x = 1. The output buffer is disabled. The
feedback signal is an adjacent I/O pin.
Combinatorial I/O in a Non-Registered Device
The control settings are SG0 = 1, SG1 = 1, and SL0x = 1. Only seven product terms are available
to the OR gate. The eighth product term is used to enable the output buffer. The signal at the
I/O pin is fed back to the AND array via the feedback multiplexer. This allows the pin to be used
as an input.
Combinatorial I/O in a Registered Device
The control bit settings are SG0=0,SG1=1 and SL0x =1. Only seven product terms are available
to the OR gate. The eighth product term is used as the output enable. The feedback signal is the
corresponding I/O signal.
Table 1. Macrocell Configuration
Cell
SG0 SG1 SL0X Configuration
Devices
Emulated
Cell
SG0 SG1 SL0X Configuration
Devices
Emulated
Device Uses Registers
Device Uses No Registers
0
1
0
Registered Output
PAL20R8, 20R6,
20R4
1
0
0
Combinatorial
Output
PAL20L2, 18L4,
16L6, 14L8
0
1
1
Combinatorial
I/O
PAL20R6, 20R4
1
0
1
Input PAL20L2, 18L4, 16L6
1
1
1
Combinatorial
I/O
PAL20L8
PALCE20V8 Family
5
5 Page 
CAPACITANCE 1
Parameter
Symbol
Parameter Description
Test Conditions
Typ Unit
CIN Input Capacitance
COUT Output Capacitance
VIN = 2.0 V
VOUT = 2.0 V
VCC = 5.0 V, TA = 25°C,
f = 1 MHz
5 pF
8 pF
Note:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where
capacitance may be affected.
SWITCHING CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES 1
Parameter
Symbol
Parameter Description
-5
Min2 Max
-7
Min2 Max
-10
Min2 Max
Unit
tPD
tS
tH
tCO
tSKEWR
tWL
tWH
fMAX
tPZX
tPXZ
tEA
tER
Input or Feedback to Combinatorial Output
Setup Time from Input or Feedback to Clock
Hold Time
Clock to Output
Skew Between Registered Outputs (Note 3)
LOW
Clock Width
HIGH
Maximum
Frequency
(Note 4)
External Feedback
Internal Feedback
(fCNT)
No Feedback
OE to Output Enable
1/(tS+tCO)
1/(tS+tCF) (Note 5)
1/(tWH+tWL)
OE to Output Disable
Input to Output Enable Using Product Term Control
Input to Output Disable Using Product Term Control
1
3
0
1
3
3
142.8
166
166
1
1
2
2
5
4
1
6
5
6
5
3 7.5 3 10 ns
5 7.5 ns
0 0 ns
1 5 3 7.5 ns
1 1 ns
4 6 ns
4 6 ns
100 66.7 MHz
125 71.4 MHz
125 83.3 MHz
1 6 2 10 ns
1 6 2 10 ns
3 9 3 10 ns
3 9 3 10 ns
Notes:
1. See “Switching Test Circuit” for test conditions.
2. Output delay minimums for tPD, tCO, tPZX, tPXZ, tEA, and tER are defined under best case conditions. Future process improvements
may alter these values; therefore, minimum values are recommended for simulation purposes only.
3. Skew testing takes into account pattern and switching direction differences between outputs that have equal loading.
4. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where
frequency may be affected.
5. tCF is a calculated value and is not guaranteed. tCF can be found using the following equation:
tCF = 1/fMAX (internal feedback) – tS.
PALCE20V8H-5/7/10 (Com’l)
11
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| PDF Descargar | [ Datasheet PALCE20V8.PDF ] | |
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