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PDF RFT2P03L Data sheet ( Hoja de datos )
| Número de pieza | RFT2P03L | |
| Descripción | 2.1A/ 30V/ 0.150 Ohm/ P-Channel Logic Level/ Power MOSFET | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Data Sheet
RFT2P03L
July 1999
File Number 4574.2
2.1A, 30V, 0.150 Ohm, P-Channel Logic
Level, Power MOSFET
This product is a P-Channel power MOSFET manufactured
using the MegaFET process. This process, which uses
feature sizes approaching those of LSI circuits, gives
optimum utilization of silicon, resulting in outstanding
performance. It was designed for use in applications such as
switching regulators, switching converters, motor drivers,
and relay drivers. This transistor can be operated directly
from integrated circuits.
Formerly developmental type TA49222.
Ordering Information
PART NUMBER
PACKAGE
BRAND
RFT2P03L
SOT-223
2P03L
NOTE: RFT2P03L is available only in tape and reel. Use the entire
part number and add the suffix T.
Features
• 2.1A, 30V
• rDS(ON) = 0.150Ω
• Temperature Compensating PSPICE® Model
• Thermal Impedance SPICE Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
Packaging
DRAIN
(FLANGE)
SOT-223
SOURCE
DRAIN
GATE
7-7-19
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1 page  
RFT2P03L
Typical Performance Curves Unless Otherwise Specified (Continued)
750
CISS
600
VGS = 0V, f = 0.1MHz
CISS = CGS + CGD
450 CRSS = CGD
COSS
COSS ≈ CDS + CGD
300
150
0
0
CRSS
-5 -10 -15 -20 -25
VDS, DRAIN TO SOURCE VOLTAGE (V)
-30
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
-10
WAVEFORMS IN
DESCENDING ORDER:
-8
ID = 2.1A
ID = 1A
-6
VDD = -15V
-4
-2
0
0 3 6 9 12 15
Qg, GATE CHARGE (nC)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
Test Circuits and Waveforms
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VGS
tP
RG
VDS
L
DUT
-
VDD
+
IAS
0.01Ω
tAV
0
VDD
IAS
tP
BVDSS
VDS
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
VGS
Ig(REF)
VDS
RL
DUT
-
VDD
+
FIGURE 16. GATE CHARGE TEST CIRCUIT
0
VGS= -2V
-VGS
VDD
0
Ig(REF)
Qg(TH)
VDS
Qg(-10)
VGS= -10V
Qg(TOT)
VGS= -20V
FIGURE 17. GATE CHARGE WAVEFORM
7-7-23
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet RFT2P03L.PDF ] | |
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