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PDF RFP8P06E Data sheet ( Hoja de datos )

Número de pieza RFP8P06E
Descripción 8A/ 60V/ 0.300 Ohm/ P-Channel Power MOSFETs
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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RFD8P06E, RFD8P06ESM, RFP8P06E
Data Sheet
July 1999 File Number 3937.5
8A, 60V, 0.300 Ohm, P-Channel Power
MOSFETs
These are P-Channel power MOSFETs manufactured using
the MegaFET process. This process, which uses feature
sizes approaching those of LSI integrated circuits gives
optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers, relay drivers and emitter switches for bipolar
transistors. These transistors can be operated directly from
integrated circuits.
The RFD8P06E, RFD8P06ESM and RFP8P06E incorporate
ESD protection and are designed to withstand 2kV (Human
Body Model) of ESD.
Formerly developmental type TA49044.
Ordering Information
PART NUMBER
PACKAGE
BRAND
RFP8P06E
TO-220AB
RFP8P06E
RFD8P06ESM
TO-252AA
D8P06E
RFD8P06E
TO-251AA
D8P06E
NOTE: When ordering, use the entire part number. Add the suffix 9A
to obtain the TO-252AA variant in tape and reel, i.e.
RFD8P06ESM9A.
Packaging
JEDEC TO-220AB
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
Features
• 8A, 60V
• rDS(ON) = 0.300
• Temperature Compensating PSPICE® Model
• 2kV ESD Protected
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
JEDEC TO-251AA
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
JEDEC TO-252AA
DRAIN (FLANGE)
GATE
SOURCE
4-117
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999.

1 page




RFP8P06E pdf
RFD8P06E, RFD8P06ESM, RFP8P06E
Typical Performance Curves Unless Otherwise Specified (Continued)
1000
VGS = 0V, f = 1MHz
800
600
CISS
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS CDS + CGS
400
200
0
0
COSS
CRSS
-5 -10 -15 -20
VDS, DRAIN TO SOURCE VOLTAGE (V)
-25
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
-60
VDD = BVDSS
-45
VDD = BVDSS
RL = 1.2
-30 IG(REF) = 1.45mA
0.75 BVDSS 0.75 BVDSS
0.50 BVDSS 0.50 BVDSS
-15 0.25 BVDSS 0.25 BVDSS
VGS = -10V
-10.0
-7.5
-5.0
-2.5
0
IG(REF)
20
IG(ACT)
t, TIME (µs)
IG(REF)
80
IG(ACT)
0.0
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms
VARY tP TO OBTAIN
REQUIRED PEAK IAS
RG
0V
tP
-VGS
VDS
L
DUT
-
VDD
+
IAS
0.01
tAV
0
VDD
IAS
tP
BVDSS
VDS
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
0V
-VGS
VGS
RGS
RL
VDS
-
+
DUT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
tON
td(ON)
tr
0
10%
tOFF
td(OFF)
tf
10%
VDS
90%
0
10%
VGS
50%
PULSE WIDTH
90%
50%
90%
FIGURE 16. SWITCHING TIME TEST CIRCUIT
FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
4-121

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