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Número de pieza | RFP3055LE | |
Descripción | 11A/ 60V/ 0.107 Ohm/ Logic Level/ N-Channel Power MOSFETs | |
Fabricantes | Intersil Corporation | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de RFP3055LE (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
No Preview Available ! RFD3055LE, RFD3055LESM, RFP3055LE
Data Sheet
November 1999 File Number 4044.3
11A, 60V, 0.107 Ohm, Logic Level,
N-Channel Power MOSFETs
These N-Channel enhancement-mode power MOSFETs are
manufactured using the latest manufacturing process
technology. This process, which uses feature sizes
approaching those of LSI circuits, gives optimum utilization
of silicon, resulting in outstanding performance. They were
designed for use in applications such as switching
regulators, switching converters, motor drivers and relay
drivers. These transistors can be operated directly from
integrated circuits.
Formerly developmental type TA49158.
Ordering Information
PART NUMBER
PACKAGE
BRAND
RFD3055LE
TO-251AA
F3055L
RFD3055LESM
TO-252AA
F3055L
RFP3055LE
TO-220AB
FP3055LE
NOTE: When ordering, use the entire part number. Add the suffix, 9A,
to obtain the TO-252 variant in tape and reel, e.g. RFD3055LESM9A.
Packaging
JEDEC TO-220AB
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
Features
• 11A, 60V
• rDS(ON) = 0.107Ω
• Temperature Compensating PSPICE® Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
JEDEC TO-251AA
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
JEDEC TO-252AA
DRAIN (FLANGE)
GATE
SOURCE
6-1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
1-888-INTERSIL or 407-727-9207 | Copyright © Intersil Corporation 1999
1 page RFD3055LE, RFD3055LESM, RFP3055LE
Typical Performance Curves Unless Otherwise Specified (Continued)
1.2 1.2
VGS = VDS, ID = 250µA
ID = 250µA
1.0 1.1
0.8 1.0
0.6
-80
-40 0
40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
200
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
1000
CISS = CGS + CGD
COSS ≅ CDS + CGD
100
10
0.1
VGS = 0V, f = 1MHz
CRSS = CGD
1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)
60
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
VDS
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
tP
0V
RG
L
DUT
+
VDD
-
IAS
0.01Ω
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
6-5
0.9
-80
-40 0
40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
200
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
10
VDD = 30V
8
6
4 WAVEFORMS IN
DESCENDING ORDER:
2 ID = 11A
ID = 5A
ID = 3A
0
0 2 4 6 8 10
Qg, GATE CHARGE (nC)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
tP
IAS
BVDSS
VDS
VDD
0
tAV
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
5 Page |
Páginas | Total 8 Páginas | |
PDF Descargar | [ Datasheet RFP3055LE.PDF ] |
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