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PDF RFG50N05L Data sheet ( Hoja de datos )

Número de pieza RFG50N05L
Descripción 50A/ 50V/ 0.022 Ohm/ Logic Level/ N-Channel Power MOSFETs
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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Data Sheet
RFG50N05L, RFP50N05L
January 2002
50A, 50V, 0.022 Ohm, Logic Level,
N-Channel Power MOSFETs
These are logic-level N-channel power MOSFETs
manufactured using the MegaFET process. This process,
which uses feature sizes approaching those of LSI
integrated circuits gives optimum utilization of silicon,
resulting in outstanding performance. They were designed
for use with logic-level (5V) driving sources in applications
such as programmable controllers, automotive switching,
switching regulators, switching converters, motor relay
drivers and emitter switches for bipolar transistors. This
performance is accomplished through a special gate oxide
design which provides full rated conductance at gate bias in
the 3V - 5V range, thereby facilitating true on-off power
control directly from integrated circuit supply voltages.
Formerly developmental type TA09872.
Ordering Information
PART NUMBER
PACKAGE
BRAND
RFG50N05L
TO-247
RFG50N05L
RFP50N05L
TO-220AB
RFP50N05L
NOTE: When ordering, use the entire part number. Add the suffix 9A to
obtain the TO-263AB variant in the tape and reel, i.e., RFP50N05L9A.
Packaging
JEDEC STYLE TO-247
DRAIN
(BOTTOM
SIDE METAL)
SOURCE
DRAIN
GATE
Features
• 50A, 50V
• rDS(ON) = 0.022
• UIS SOA Rating Curve (Single Pulse)
• Design Optimized for 5V Gate Drive
• Can be Driven Directly from CMOS, NMOS, TTL Circuits
• Compatible with Automotive Drive Requirements
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
• Majority Carrier Device
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
JEDEC TO-220AB
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
©2002 Fairchild Semiconductor Corporation
RFG50N05L, RFP50N05L Rev. B

1 page




RFG50N05L pdf
Test Circuits and Waveforms
RFG50N05L, RFP50N05L
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
tP
0V
RG
VDS
L
DUT
+
VDD
-
IAS
0.01
0
tP
IAS
BVDSS
VDS
VDD
tAV
FIGURE 13. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 14. UNCLAMPED ENERGY WAVEFORMS
VDS
VGS
RGS
RL
DUT
+
VDD
-
VGS
FIGURE 15. SWITCHING TIME TEST CIRCUIT
VDS
RL
VGS
IG(REF)
DUT
+
VDD
-
FIGURE 17. GATE CHARGE TEST CIRCUIT
VDS
tON
td(ON)
tr
90%
tOFF
td(OFF)
tf
90%
10%
0
VGS
10%
0
50%
PULSE WIDTH
10%
90%
50%
FIGURE 16. RESISTIVE SWITCHING WAVEFORMS
VDD
VDS
Qg(TOT)
VGS
VGS = 1V
0
Qg(5)
Qg(TH)
VGS = 5V
VGS = 10V
IG(REF)
0
FIGURE 18. GATE CHARGE WAVEFORMS
©2002 Fairchild Semiconductor Corporation
RFG50N05L, RFP50N05L Rev. B

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