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PDF RFD3N08L Data sheet ( Hoja de datos )

Número de pieza RFD3N08L
Descripción 3A/ 80V/ 0.800 Ohm/ Logic Level/ N-Channel Power MOSFETs
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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Data Sheet
RFD3N08L, RFD3N08LSM
July 1999 File Number 2836.4
3A, 80V, 0.800 Ohm, Logic Level,
N-Channel Power MOSFETs
The RFD3N08L and RFD3N08LSM are N-Channel
enhancement mode silicon gate power field effect transistors
specifically designed for use with logic level (5V) driving
sources in applications such as programmable controllers,
automotive switching, and solenoid drivers. This
performance is accomplished through a special gate oxide
design which provides full rated conductance at gate biases
in the 3V to 5V range, thereby facilitating true on-off power
control directly from logic circuit supply voltages.
Formerly developmental type TA09922.
Ordering Information
PART NUMBER
PACKAGE
BRAND
RFD3N08L
TO-251AA
F3N08L
RFD3N08LSM
TO-252AA
F3N08L
NOTE: When ordering, include the entire part number. Add the suffix 9A
to obtain the TO-252AA variant in tape and reel, i.e. RFD3N08LSM9A
Packaging
JEDEC TO-251AA
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
Features
• 3A, 80V
• rDS(ON) = 0.800
• Temperature Compensating PSPICE® Model
• On Resistance vs Gate Drive Voltage Curves
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
JEDEC TO-252AA
DRAIN
(FLANGE)
GATE
SOURCE
6-26
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999

1 page




RFD3N08L pdf
RFD3N08L, RFD3N08LSM
Typical Performance Curves Unless Otherwise Specified (Continued)
2.0
ID = 250µA
1.5
1.0
0.5
0
-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
180
CISS
150
120
COSS
90
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS CDS + CGD
60
CRSS
30
0
0 5 10 15 20 25
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
100
VDD = 40V, ID = 3A, RL = 13.3
80
tr
60
40
20
0
0
tf
td(OFF)
td(ON)
10 20 30 40
RGS, GATE TO SOURCE RESISTANCE ()
50
FIGURE 13. SWITCHING TIME vs GATE RESISTANCE
80 5.00
60 3.75
RL = 26.67
IG(REF) = 0.1mA
VGS = 5V
40 2.50
PLATEAU VOLTAGES IN
DESCENDING ORDER:
VDD = BVDSS
20
VDD = 0.75 BVDSS
VDD = 0.50 BVDSS
1.25
VDD = 0.25BVDSS
0
20
IG(REF)
IG(ACT)
t, TIME (µs)
80
IG(REF)
IG(ACT)
0
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
tP
0V
RG
VDS
L
DUT
+
VDD
-
IAS
0.01
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
tP
IAS
BVDSS
VDS
VDD
0
tAV
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
6-30

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