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PDF RFD16N03 Data sheet ( Hoja de datos )

Número de pieza RFD16N03
Descripción 16A/ 30V/ 0.025 Ohm/ Logic Level/ N-Channel Power MOSFETs
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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Data Sheet
RFD16N03L, RFD16N03LSM
April 1999 File Number 4013.2
16A, 30V, 0.025 Ohm, Logic Level,
N-Channel Power MOSFETs
These are N-Channel power MOSFETs manufactured using
the MegaFET process. This process, which uses feature
sizes approaching those of LSI circuits, gives optimum
utilization of silicon, resulting in outstanding performance.
They were designed for use in applications such as
switching regulators, switching converters, motor drivers and
relay drivers. This performance is accomplished through a
special gate oxide design which provides full rated
conductance at gate bias in the 3V to 5V range, thereby
facilitating true on-off power control directly from logic level
(5V) integrated circuits.
Formerly developmental type TA49030.
Ordering InformationS
PART NUMBER
PACKAGE
BRAND
RFD16N03L
TO-251AA
16N03L
RFD16N03LSM
TO-252AA
16N03L
NOTE: When ordering, use the entire part number. Add the suffix 9A,
to obtain the TO-252AA variant in tape and reel, e.g. RFD16N03LSM9A.
Features
• 16A, 30V
• rDS(ON) = 0.025
• Temperature Compensating PSPICE™ Model
• Can be Driven Directly from CMOS, NMOS,
and TTL Circuits
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
DRAIN
GATE
SOURCE
Packaging
DRAIN
(FLANGE)
JEDEC TO-251AA
SOURCE
DRAIN
GATE
JEDEC TO-252AA
DRAIN
(FLANGE)
GATE
SOURCE
6-156
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE™ is a trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999

1 page




RFD16N03 pdf
RFD16N03L, RFD16N03LSM
Typical Performance Curves Unless Otherwise Specified (Continued)
2.0 VGS = VDS, ID = 250µA
1.5
2.0
ID = 250µA
1.5
1.0 1.0
0.5 0.5
0
-80 -40
0
40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
2500
VGS = 0V, f = 1MHz
2000
CISS
1500
1000
500
0
0
CISS = CGS + CGD
CRSS = CGD
COSS CDS + CGD
COSS
CRSS
5
10 15
20
VDS, DRAIN TO SOURCE VOLTAGE (V)
25
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
VDS
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
tP
0V
RG
L
DUT
+
VDD
-
IAS
0.01
0
-80 -40
0
40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
30
VDD = BVDSS
24
VDD = BVDSS
5
4
18 3
12
0.75 BVDSS
0.50 BVDSS
0.25 BVDSS
2
6
RL = 1.875
IG(REF) = 0.6mA
1
VGS = 5V
00
IG(REF)
IG(REF)
20
IG(ACT)
t, TIME (s)
80
IG(ACT)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
tP
IAS
BVDSS
VDS
VDD
0
tAV
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
6-160

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