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PDF RFD14N06LSM Data sheet ( Hoja de datos )
| Número de pieza | RFD14N06LSM | |
| Descripción | 14A/ 60V/ 0.100 Ohm/ Logic Level/ N-Channel Power MOSFETs | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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RFD14N06L, RFD14N06LSM, RFP14N06L
Data Sheet
July 1999 File Number 4088.3
14A, 60V, 0.100 Ohm, Logic Level,
N-Channel Power MOSFETs
These are N-Channel power MOSFETs manufactured using
the MegaFET process. This process, which uses feature
sizes approaching those of LSI integrated circuits, gives
optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers and relay drivers. This performance is accomplished
through a special gate oxide design which provides full rated
conductance at gate bias in the 3V - 5V range, thereby
facilitating true on-off power control directly from logic level
(5V) integrated circuits.
Formerly developmental type TA09870.
Ordering Information
PART NUMBER
PACKAGE
BRAND
RFD14N06L
TO-251AA
14N06L
RFD14N06LSM
TO-252AA
14N06L
RFP14N06L
TO-220AB
FP14N06L
NOTE: When ordering, use the entire part number. Add the suffix 9A, to
obtain the TO-252AA variant in tape and reel, i.e. RFD14N06LSM9A.
Packaging
JEDEC TO-251AA
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
Features
• 14A, 60V
• rDS(ON) = 0.100Ω
• Temperature Compensating PSPICE® Model
• Can be Driven Directly from CMOS, NMOS, and TTL
Circuits
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
JEDEC TO-252AA
DRAIN (FLANGE)
GATE
SOURCE
JEDEC TO-220AB
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
6-1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1 page  
RFD14N06L, RFD14N06LSM, RFP14N06L
Typical Performance Curves Unless Otherwise Specified (Continued)
2.0
VGS = VDS, ID = 250µA
1.5
2.0
ID = 250µA
1.5
1.0
0.5
0
-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
800
600
400
200
0
0
CISS
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
COSS
CRSS
5 10 15 20
VDS, DRAIN TO SOURCE VOLTAGE (V)
25
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VGS
tP
0V
RG
VDS
L
DUT
+
VDD
-
IAS
0.01Ω
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
6-5
1.0
0.5
0
-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
60
VDD = BVDSS
45
VDD = BVDSS
10
7.5
30 5.0
0.75 BVDSS
15
0.50
0.25
BBVVDDSSSS
2.5
RL = 3.57Ω
IG(REF) = 0.4mA
VGS = 5V
00
20 I-I-GG-----((--AR----CE----FT----))
t, TIME (ms)
80 I-I-GG-----((--AR----CE----FT----))
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
tP
IAS
BVDSS
VDS
VDD
0
tAV
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet RFD14N06LSM.PDF ] | |
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