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PDF RF2968 Data sheet ( Hoja de datos )

Número de pieza RF2968
Descripción BLUETOOTHTM TRANSCEIVER
Fabricantes RF Micro Devices 
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Preliminary
11
RF2968
BLUETOOTHTM TRANSCEIVER
Typical Applications
Bluetooth GSM/GPRS/EDGE Cellular
Phones
Bluetooth Wireless LAN
• Cordless Phones
• Battery-Powered Portable Devices
Product Description
The RF2968 is a monolithic integrated circuit intended for
use as a low-cost FSK transceiver in Bluetooth applica-
tions. The device is provided in 32-lead plastic LPCC
packaging and is designed to provide a fully-functional
FSK transceiver. The chip is intended for Bluetooth appli-
cations in the 2.4GHz to 2.5GHz ISM band. The IF and
demodulation sections of the chip require no external fil-
ters or discriminators. The chip also features an image
reject front end and a fully programmable synthesizer
with integrated oscillator circuitry. Self-calibrating RX and
TX IF circuitry optimizes link performance and eliminates
manufacturing variations.
BLUETOOTH is a trademark owned by the Bluetooth SIG, Inc., and licensed
to RF Micro Devices, Inc.
Optimum Technology Matching® Applied
Si BJT
üSi Bi-CMOS
GaAs HBT
SiGe HBT
GaAs MESFET
Si CMOS
VCC1 1
VCC2 2
TXOUT 3
RXIN 4
VCC3 5
VCC4 6
LPO 7
DVDDH 8
32 31 30 29 28 27 26
25
Transmitter
Filter
BT = 0.5
TX
DATA
SYNC
Σ /4
4 MHz LOOP
ICO FILTER
APPF
LO
Phase
/4
Detector /
Charge
Pump
1 MHz
Voltage
Regulator
VCO
Phase Detector/
Charge Pump
LO x2
Prescaler
16/17
Synthesizer
Address 7
500 kHz
TX DATA
1 MHz IF
Σ
Receiver
FSK Demodulator
LPF/
Equalizer
16 Address 4
16 Address 5
16 Address 6
BDATA1
10 MHz
BPKTCTL
BXTLEN
Chip
Control
DBus
Address 30
Address 31
16-Bit Shift
Register
(Read Only)
Address 3
5
25 25-Bit Shift
Register
25-Bit Latch
(Write Only)
25
APPF
LO
Clock / Data
Recovery
500 kHz
1 MHz
/2
Div R
24 PLLGND
23 BnPWR
22 BDCLK
21 BDDATA
20 BnDEN
19 OSC I
60 MHz
10 MHz
12 MHz
/6
/5
Ref. Osc.
/60
Phase Detector/
Charge Pump
Div R
18 OSC O
17 BRCLK
9 10 11 12 13 14 15
16
5.00
± 0.10
4.75
± 0.10
-A-
0.40 ± 0.10
-B-
4.75 5.00
± 0.10 ± 0.10
0.20
1.0
MAX
11° ± 1°
(4X)
See Detail A
0.70 ± 0.08
-C-
0.50
Seating
Plane
NOTES:
1. Shaded lead indicates Pin 1.
2. Package surface roughness at 1.5 µm ± 0.30.
Detail A
0.70 ±
0.08 1.00
MAX
5 µm - 20 µm
-C-
Package Style: LCC, 32-Pin, 5x5
Features
• Fully Monolithic Integrated Transceiver
• Self-Calibrating Transceiver
• Image Reject Receiver
Bluetooth and BlueRF compatible
• Supports Reference Clocks to 40MHz
• Smallest Footprint Bluetooth Transceiver
Ordering Information
TBD
11
Functional Block Diagram
Rev A13 010912
RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA
Tel (336) 664 1233
Fax (336) 664 0454
http://www.rfmd.com
11-117

1 page




RF2968 pdf
Preliminary
RF2968
Pin Function Description
Interface Schematic
1
VCC1
Supply voltage for the VCO doubler and LO amplifier circuits.
2
VCC2
Supply voltage for the RX mixers, TX PA, and LNA bias circuits.
3 TX OUT Transmitter output. TX OUT output impedance is 50(nominal) when
the transmitter is enabled. TX OUT is a high impedance when the
transmitter is disabled. Because this pin is DC-biased, an external cou-
pling capacitor is required.
VCC
10
TX OUT
4
RX IN
Receiver input. RX IN input impedance is a low impedance when the
receiver is enabled. RX IN is a high impedance when the receiver is
disabled. An internal series inductor is used to tune the input imped-
RX IN
ance.
5
VCC3
Supply voltage for the RX input stage (LNA).
VCC3
VCC3
6
VCC4
Supply voltage for the TX mixers and bias circuits of the LO amplifier,
LNA, and RX mixers.
7
LPO
Low frequency clock output for low power mode. In sleep mode, this pin
may provide either a 3.2kHz or 32kHz clock having a 50% duty cycle to
the baseband. In other modes, the output is disabled.
8 DVDDH Supply voltage for the RX IF VGA circuit.
9
IREF
Connects an external precision resistor (1% tolerance) for generation
of a constant current reference.
10
VCC5
Supply voltage for the analog IF circuits.
11 D1 This is the output of the charge pump for clock recovery circuit. A RC See pin 26.
network from this pin to ground is used to establish the PLL bandwidth.
12 BPKTCTL In transmit mode, this pin is used as a strobe to enable the PA stage. In See pin 23.
receive mode, the baseband has the option to use this pin to signal the
detection of the sync word. The baseband drives this pin high at the
end of the sync word, at which time a second DC estimation is per-
formed by sampling the trailer bits. If baseband control is not desired to
signal the second DC estimation, then an internal timer is used to mark
the end of the sync word. The BBC bit is used to select the baseband
control option; the default setting uses the internal timer.
13 BDATA1 Input data to transmitter/output data from receiver. The input data is RXDATA
unfiltered data at 1MHz data rate. The pin is bidirectional, switching
between data in and data out modes during Transmit and Receive
modes respectively.
TX DATA
14 RECCLK Recovered clock output.
See pin 17.
15 RECDATA Recovered data output.
See pin 17.
16 BXTLEN This pin is part of the chip power control circuit. It is used to enable/dis-
able “sleep” mode of chip.
BXTLEN
BDATA1
VCC
11
Rev A13 010912
11-121

5 Page





RF2968 arduino
Preliminary
RF2968
Evaluation Board Schematic
(Download Bill of Materials from www.rfmd.com.)
VCC
RX IN/TX OUT
VCC
LPO
VCC
C1*
22 nF
C2
FL1 22 nF
C3*
22 nF
R6
820
C13
1 µF
C12
1 µF
L2 L1
3.9 nH 3.9 nH
32 31 30 29 28 27
1
R5
43 k
R4
20 k
C11
330 pF
BDCLK
BDDATA
BnDEN
BRCLK
VCC
BXTLEN
RECDATA
RECCLK
C10
30 pF
BPKTCTL
26 25
24
C9*
22 nF
P1
10 20
9 19
8 18
7 17
6 16
5 15
4 14
3 13
2 12
1 11
CON20
BnPWR
BDATA1
VCC
LPO
VCC
2 23 BnPWR
3 22 BDCLK
4 21 BDDATA
5 20 BnDEN
6 19
R3 Y1 C8
7 18 470 k13 MHz 47 pF
8
9
17
10 11 12 13 14 15 16
R1
20 k
1%
C7
47 pF
BRCLK
BXTLEN
RECDATA
RECCLK
BDATA1
BPKTCTL
C4*
22 nF
*Note: Required supply filtering may vary depending on implementation.
C5
100 pF
C6
2.7 nF
R2
22 k
11
Rev A13 010912
11-127

11 Page







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