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PDF RLP03N06CLE Data sheet ( Hoja de datos )
| Número de pieza | RLP03N06CLE | |
| Descripción | 0.3A/ 60V/ 6 Ohm/ ESD Rated/ Current Limited/ Voltage Clamped/ Logic Level N-Channel Power MOSFETs | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Data Sheet
RLD03N06CLE, RLD03N06CLESM,
RLP03N06CLE
July 1999 File Number 3948.5
0.3A, 60V, 6 Ohm, ESD Rated, Current
Limited, Voltage Clamped, Logic Level
N-Channel Power MOSFETs
These are intelligent monolithic power circuits which
incorporate a lateral bipolar transistor, resistors, zener
diodes and a power MOS transistor. The current limiting of
these devices allow it to be used safely in circuits where a
shorted load condition may be encountered. The drain to
source voltage clamping offers precision control of the circuit
voltage when switching inductive loads. The “Logic Level”
gate allows this device to be fully biased on with only 5V
from gate to source, thereby facilitating true on-off power
control directly from logic level (5V) integrated circuits.
These devices incorporate ESD protection and are designed
to withstand 2kV (Human Body Model) of ESD.
Formerly developmental type TA49028.
Ordering Information
PART NUMBER
PACKAGE
BRAND
RLD03N06CLE
TO-251AA
03N06C
RLD03N06CLESM TO-252AA
03N06C
RLP03N06CLE
TO-220AB
03N06CLE
NOTE: When ordering, use the entire part number. Add the suffix 9A to
obtain the TO-252AA variant in tape and reel, i.e. RLD03N06CLESM9A.
Packaging
JEDEC TO-251AA
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
Features
• 0.30A, 60V
• rDS(ON) = 6.0Ω
• Built in Current Limit ILIMIT 0.140 to 0.210A at 150oC
• Built in Voltage Clamp
• Temperature Compensating PSPICE® Model
• 2kV ESD Protected
• Controlled Switching Limits EMI and RFI
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
D
G
S
JEDEC TO-252AA
DRAIN
(FLANGE)
GATE
SOURCE
DRAIN
(FLANGE)
JEDEC TO-220AB
SOURCE
DRAIN
GATE
6-418
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1 page  
RLD03N06CLE, RLD03N06CLESM, RLP03N06CLE
Typical Performance Curves Unless Otherwise Specified (Continued)
60
5.00
45
VDD = BVDSS
3.75
30 2.50
0.75 BVDSS
RL = 600Ω
IG(REF) = 0.1mA
15
0.50 BVDSS
0.25 BVDSS
VGS = 5V
1.25
0
10 I-I-GG-----((--AR----CE----FT----))
t, TIME (µs) 40 I-I-GG-----((--AR----CE----FT----))
0.00
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT.
Test Circuits and Waveforms
VDD
RL
VDS
VDS
tON
td(ON)
tr
90%
tOFF
td(OFF)
tf
90%
VGS
0V
RGS
DUT
10%
VGS
10%
50%
PULSE WIDTH
10%
90%
50%
FIGURE 13. RESISTIVE SWITCHING TEST CIRCUIT
Detailed Description
Temperature Dependence of Current Limiting and
Switching Speed Performance
The RLD03N06CLE, CLESM and RLP03N06CLE are
monolithic power devices which incorporate a Logic Level power
MOSFET transistor with a current sensing scheme and control
circuitry to enable the device to self limit the drain source current
flow. The current sensing scheme supplies current to a resistor
that is connected across the base to emitter of a bipolar transistor
in the control section. The collector of this bipolar transistor is
connected to the gate of the power MOSFET transistor. When
the ratiometric current from the current sensing reaches the
value required to forward bias the base emitter junction of this
bipolar transistor, the bipolar “turns on”. A resistor is incorporated
in series with the gate of the power MOSFET transistor allowing
the bipolar transistor to adjust the drive on the gate of the power
MOSFET transistor to a voltage which then maintains a constant
current in the power MOSFET transistor. Since both the
ratiometric current sensing scheme and the base emitter unction
FIGURE 14. RESISTIVE SWITCHING WAVEFORMS
voltage of the bipolar transistor vary with temperature, the current
at which the device limits is a function of temperature. This
dependence is shown in Figure 3.
The resistor in series with the gate of the power MOSFET
transistor also results in much slower switching performance
than in standard power MOSFET transistors. This is an
advantage where fast switching can cause EMI or RFI. The
switching speed is very predictable.
DC Operation
The limit on the drain to source voltage for operation in
current limiting on a steady state (DC) basis is shown in the
equation below. The dissipation in the device is simply the
applied drain to source voltage multiplied by the limiting
current. This device, like most power MOSFET devices
today, is limited to 175oC. The maximum voltage allowable
can, therefore, be expressed as shown in Equation 1:
DS = (--I-1-L--5-M---0---•°---C-(--R--–--θ-T--J--A-C---M---+--B--R--I--Eθ---J-N--A--T--)--)
(EQ. 1)
6-422
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet RLP03N06CLE.PDF ] | |
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