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PDF PA28F004S3-120 Data sheet ( Hoja de datos )

Número de pieza PA28F004S3-120
Descripción BYTE-WIDE SMART 3 FlashFile MEMORY FAMILY 4/ 8/ AND 16 MBIT
Fabricantes Intel Corporation 
Logotipo Intel Corporation Logotipo



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E
PRELIMINARY
BYTE-WIDE
SMART 3 FlashFile™ MEMORY FAMILY
4, 8, AND 16 MBIT
28F004S3, 28F008S3, 28F016S3
Includes Commercial and Extended Temperature Specifications
n SmartVoltage Technology
Smart 3 Flash: 2.7 V or 3.3 V VCC
and 2.7 V, 3.3 V or 12 V VPP
n High-Performance
120 ns Read Access Time
n Enhanced Data Protection Features
Absolute Protection with VPP = GND
Flexible Block Locking
Block Write Lockout during Power
Transitions
n Enhanced Automated Suspend Options
Program Suspend to Read
Block Erase Suspend to Program
Block Erase Suspend to Read
n Industry-Standard Packaging
40-Lead TSOP, 44-Lead PSOP
and 40 Bump µBGA* CSP
n High-Density 64-Kbyte Symmetrical
Erase Block Architecture
4 Mbit: Eight Blocks
8 Mbit: Sixteen Blocks
16 Mbit: Thirty-Two Blocks
n Extended Cycling Capability
100,000 Block Erase Cycles
n Low Power Management
Deep Power-Down Mode
Automatic Power Savings Mode
Decreases ICC in Static Mode
n Automated Program and Block Erase
Command User Interface
Status Register
n SRAM-Compatible Write Interface
n ETOX™ V Nonvolatile Flash
Technology
Intel’s byte-wide Smart 3 FlashFile™ memory family renders a variety of density offerings in the same
package. The 4-, 8-, and 16-Mbit byte-wide FlashFile memories provide high-density, low-cost, nonvolatile,
read/write storage solutions for a wide range of applications. Their symmetrically-blocked architecture, flexible
voltage, and extended cycling provide highly flexible components suitable for resident flash arrays, SIMMs,
and memory cards. Enhanced suspend capabilities provide an ideal solution for code or data storage
applications. For secure code storage applications, such as networking, where code is either directly
executed out of flash or downloaded to DRAM, the 4-, 8-, and 16-Mbit FlashFile memories offer three levels
of protection: absolute protection with VPP at GND, selective hardware block locking, or flexible software
block locking. These alternatives give designers ultimate control of their code security needs.
This family of products is manufactured on Intel’s 0.4 µm ETOX™ V process technology. They come in
industry-standard packages: the 40-lead TSOP, ideal for board-constrained applications, and the rugged
44-lead PSOP. Based on the 28F008SA architecture, the byte-wide Smart 3 FlashFile memory family
enables quick and easy upgrades for designs that demand state-of-the-art technology.
December 1997
Order Number: 290598-004

1 page




PA28F004S3-120 pdf
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BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY
1.0 INTRODUCTION
This datasheet contains 4-, 8-, and 16-Mbit Smart 3
FlashFile memory specifications. Section 1.0
provides a flash memory overview. Sections 2.0,
3.0, 4.0, and 5.0 describe the memory organization
and functionality. Section 6.0 covers electrical
specifications for commercial and extended
temperature product offerings. Ordering information
is provided in Section 7.0. Finally, the byte-wide
Smart 3 FlashFile memory family documentation
also includes application notes and design tools
which are referenced in Section 8.0.
1.1 New Features
The byte-wide Smart 3 FlashFile memory family
maintains backwards-compatibility with Intel’s
28F008SA-L. Key enhancements include:
SmartVoltage Technology
Enhanced Suspend Capabilities
In-System Block Locking
They share a compatible status register, software
commands, and pinouts. These similarities enable
a clean upgrade from the 28F008SA-L to byte-wide
Smart 3 FlashFile products. When upgrading, it is
important to note the following differences:
Because of new feature and density options,
the devices have different device identifier
codes. This allows for software optimization.
VPPLK has been lowered from 6.5 V to 1.5 V to
support low VPP voltages during block erase,
program, and lock-bit configuration operations.
Designs that switch VPP off during read
operations should transition VPP to GND.
To take advantage of SmartVoltage tech-
nology, allow VPP connection to 3.3 V.
For more details see application note AP-625,
28F008SC Compatibility with 28F008SA (order
number 292180).
1.2 Product Overview
The byte-wide Smart 3 FlashFile memory family
provides density upgrades with pinout compatibility
for the 4-, 8-, and 16-Mbit densities. The 28F004S3,
28F008S3, and 28F016S3 are high-performance
memories arranged as 512 Kbyte, 1 Mbyte, and
2 Mbyte of eight bits. This data is grouped in eight,
sixteen, and thirty-two 64-Kbyte blocks which are
individually erasable, lockable, and unlockable in-
system. Figure 5 illustrates the memory
organization.
SmartVoltage technology enables fast factory
programming and low power designs. Specifically
designed for 3 V systems, Smart 3 FlashFile
components support read operations at 2.7 V and
3.3 V VCC and block erase and program operations
at 2.7 V, 3.3 V and 12 V VPP. The 12 V VPP option
renders the fastest program performance which will
increase your factory throughput. With the 2.7 V or
3.3 V VPP option, VCC and VPP can be tied together
for a simple, low-power 2.7 V or 3 V design. In
addition to the voltage flexibility, the dedicated VPP
pin gives complete data protection when VPP
VPPLK.
Internal VPP detection circuitry automatically
configures the device for optimized block erase and
program operations.
A Command User Interface (CUI) serves as the
interface between the system processor and
internal operation of the device. A valid command
sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for block erase, program, and lock-bit
configuration operations.
A block erase operation erases one of the device’s
64-Kbyte blocks typically within 1.1 second
(12 V VPP), independent of other blocks. Each block
can be independently erased 100,000 times
(1.6 million block erases per device). A block erase
suspend operation allows system software to
suspend block erase to read data from or program
data to any other block.
Data is programmed in byte increments typically
within 7.6 µs (12 V VPP). A program suspend
operation permits system software to read data or
execute code from any other flash memory array
location.
PRELIMINARY
5

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PA28F004S3-120 arduino
E
BYTE-WIDE SMART 3 FlashFile™ MEMORY FAMILY
2.0 PRINCIPLES OF OPERATION
The byte-wide Smart 3 FlashFile memories include
an on-chip WSM to manage block erase, program,
and lock-bit configuration functions. It allows for:
100% TTL-level control inputs, fixed power supplies
during block erasure, program, and lock-bit
configuration, and minimal processor overhead with
RAM-like interface timings.
After initial device power-up or return from deep
power-down mode (see Bus Operations), the
device defaults to read array mode. Manipulation of
external memory control pins allow array read,
standby, and output disable operations.
Status register and identifier codes can be
accessed through the CUI independent of the VPP
voltage. High voltage on VPP enables successful
block erasure, program, and lock-bit configuration.
All functions associated with altering memory
contents—block erase, program, lock-bit
configuration, status, and identifier codes—are
accessed via the CUI and verified through the
status register.
Commands are written using standard micro-
processor write timings. The CUI contents serve as
input to the WSM that controls block erase,
program, and lock-bit configuration operations. The
internal algorithms are regulated by the WSM,
including pulse repetition, internal verification, and
margining of data. Addresses and data are
internally latched during write cycles. Writing the
appropriate command outputs array data, accesses
the identifier codes, or outputs status register data.
Interface software that initiates and polls progress
of block erase, program, and lock-bit configuration
can be stored in any block. This code is copied to
and executed from system RAM during flash
memory updates. After successful completion,
reads are again possible via the Read Array
command. Block erase suspend allows system
software to suspend a block erase to read data
from or program data to any other block. Program
suspend allows system software to suspend a
program to read data from any other flash memory
array location.
1FFFFF
1F0000
1EFFFF
1E0000
1DFFFF
1D0000
1CFFFF
1C0000
1BFFFF
1B0000
1AFFFF
1A0000
19FFFF
190000
18FFFF
180000
17FFFF
170000
16FFFF
160000
15FFFF
150000
14FFFF
140000
13FFFF
130000
12FFFF
120000
11FFFF
110000
10FFFF
100000
0FFFFF
0F0000
0EFFFF
0E0000
0DFFFF
0D0000
0CFFFF
0C0000
0BFFFF
0B0000
0AFFFF
0A0000
09FFFF
090000
08FFFF
080000
07FFFF
070000
06FFFF
060000
05FFFF
050000
04FFFF
040000
03FFFF
030000
02FFFF
020000
01FFFF
010000
00FFFF
000000
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
16-Mbit
15
14
13
12
11
10
9
8-Mbit
8
7
6
5
4
4-Mbit
3
2
1
0
Figure 5. Memory Map
PRELIMINARY
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