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PDF P90CL301BFH Data sheet ( Hoja de datos )
| Número de pieza | P90CL301BFH | |
| Descripción | Low voltage 16-bit microcontroller | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
P90CL301BFH (C100)
Low voltage 16-bit microcontroller
Preliminary specification
File under Integrated Circuits, IC17
1996 Dec 11
1 page  
Philips Semiconductors
Low voltage 16-bit microcontroller
5 PINNING INFORMATION
5.1 Pinning
ndbook, full pagewidth
AS 1
D7 2
D6 3
D5 4
D4 5
D3 6
D2 7
D1 8
D0 9
VDD3 10
XTAL1 11
VSS1 12
UDS/A0/AD0 13
A1/AD1 14
A2/AD2 15
A3/AD3 16
A4/AD4 17
A5/AD5 18
A6/AD6 19
A7/AD7 20
P90CL301BFH
Preliminary specification
P90CL301BFH (C100)
60 P15/ADC3
59 VDDA
58 BSIZE
57 P11/SDA
56 P10/SCL
55 P9/PWM1 (CP1)
54 P8/PWM0 (CP0)
53 SP0/RX1/INT0
52 SP1/TX1/INT1 (CLK0)
51 VSS2
50 SP2/RX0/INT2 (CP2)
49 SP3/TX0/INT3 (CP3)
48 SP4/INT4 (CP4)
47 SP5/INT5 (CP5)
46 SP6/INT6 (CLK1)
45 NMIN/SP7
44 CS0/FC0
43 CS1/FC1
42 CS2/FC2
41 CS3/ALE
MGD773
1996 Dec 11
Fig.2 Pinning diagram of the P90CL301BFH (LQFP80).
5
5 Page 
Philips Semiconductors
Low voltage 16-bit microcontroller
Preliminary specification
P90CL301BFH (C100)
Table 12 Bus size depending on BSIZE, CSBTX and BSn (n = 0 to 6)
PIN BSIZE BIT CSBTX
BUS SIZE OF CS0 TO CS6(1)
BSn = 0
BSn = 1
BUS SIZE OF CSBTX
AT
BOOT
AFTER
BOOT
0 0 16 bit 8 bit 16 16
0 1 16 bit 8 bit 16 8
1 0 note 2 8 bit 8 8
1 1 16 bit 8 bit 8 16
PORT PL AVAILABLE
(P0 TO P7)
no
yes
yes
no
Notes
1. Depending on bit BSn in register BSREG.
2. The default value after reset of bits BSn in register BSREG is logic 0 which corresponds to 16-bit mode for CS0 to
CS6. In this case, it is recommended to set BSn to logic 1 in the boot routine. Afterwards if CSBTX is set to logic 1,
BSn can be reset to logic 0 by software for further transfers in 16-bit mode.
6.4 System Control Register (SYSCON)
The P90CL301BFH uses a System Control Register (SYSCON) for adjusting system parameters.
Table 13 System Control Register (address FFFF 8000H)
15 14 13 12 11
10 9 8 7(1) 6(1) 5 4 3 2 1(2) 0
WDSC BPE CSBTX STBY PCLK3 PCLK2 PDE GF PCLK1 PCLK0 IM WD FBC PD IDL DOFF
Notes
1. The default values after a CPU reset: PCLK1 = 1 and PCLK0 = 1; all other SYSCON bits are a logic 0.
2. All bits are reset by the RESET instruction, except the IDL bit which is only reset by a CPU reset.
1996 Dec 11
11
11 Page | ||
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