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Número de pieza P89LPC931FDH
Descripción 8-bit microcontrollers with two-clock 80C51 core 4 kB/8 kB 3 V Flash with 256-byte data RAM
Fabricantes NXP Semiconductors 
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P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
4 kB/8 kB 3 V Flash with 256-byte data RAM
Rev. 04 — 06 January 2004
Product data
1. General description
The P89LPC930/931 is a single-chip microcontroller designed for applications
demanding high-integration, low cost solutions over a wide range of performance
requirements. The P89LPC930/931 is based on a high performance processor
architecture that executes instructions in two to four clocks, six times the rate of
standard 80C51 devices. Many system-level functions have been incorporated into
the P89LPC930/931 in order to reduce component count, board space, and system
cost.
2. Features
s A high performance 80C51 CPU provides instruction cycle times of 167-333 ns for
all instructions except multiply and divide when executing at 12 MHz. This is
6 times the performance of the standard 80C51 running at the same clock
frequency. A lower clock frequency for the same performance results in power
savings and reduced EMI.
s 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
s 4 kB/8 kB Flash code memory with 1 kB sectors, and 64-byte page size.
s Byte-erase allowing code memory to be used for data storage.
s Flash program operation completes in 2 ms.
s Flash erase operation completes in 2 ms.
s 256-byte RAM data memory.
s Two 16-bit counter/timers. Each timer may be configured to toggle a port output
upon timer overflow or to become a PWM output.
s Real-Time clock that can also be used as a system timer.
s Two analog comparators with selectable inputs and reference source.
s Enhanced UART with fractional baud rate generator, break detect, framing error
detection, automatic address detection and versatile interrupt capabilities.
s 400 kHz byte-wide I2C-bus communication port.
s SPI communication port.
s Eight keypad interrupt inputs, plus two additional external interrupt inputs.
s Four interrupt priority levels.
s Watchdog timer with separate on-chip oscillator, requiring no external
components. The Watchdog time-out time is selectable from 8 values.
s Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent
spurious and incomplete resets. A software reset function is also available.

1 page




P89LPC931FDH pdf
Philips Semiconductors
P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
5. Pinning information
5.1 Pinning
handbook, halfpage
P2.0 1
P2.1 2
KBIO/CMP2/P0.0 3
P1.7 4
P1.6 5
RST/P1.5 6
VSS 7
XTAL1/P3.1 8
CLKOUT/XTAL2/P3.0 9
INT1/P1.4 10
SDA/INT0/P1.3 11
SCL/T0/P1.2 12
MOSI/P2.2 13
MISO/P2.3 14
28 P2.7
27 P2.6
26 P0.1/CIN2B/KBI1
25 P0.2/CIN2A/KBI2
24 P0.3/CIN1B/KBI3
23 P0.4/CIN1A/KBI4
22 P0.5/CMPREF/KBI5
21 VDD
20 P0.6/CMP1/KBI6
19 P0.7/T1/KBI7
18 P1.0/TXD
17 P1.1/RXD
16 P2.5/SPICLK
15 P2.4/SS
002aaa429
Fig 2. DIP28 pin configuration.
9397 750 12284
Product data
Rev. 04 — 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
5 of 54

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P89LPC931FDH arduino
Philips Semiconductors
P89LPC930/931
8-bit microcontrollers with two-clock 80C51 core
7. Special function registers
Remark: Special Function Registers (SFRs) accesses are restricted in the following
ways:
User must not attempt to access any SFR locations not defined.
Accesses to any defined SFR locations must be strictly for the functions for the
SFRs.
SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:
‘-’ Unless otherwise specified, must be written with ‘0’, but can return any value
when read (even if it was written with ‘0’). It is a reserved bit and may be used in
future derivatives.
‘0’ must be written with ‘0’, and will return a ‘0’ when read.
‘1’ must be written with ‘1’, and will return a ‘1’ when read.
9397 750 12284
Product data
Rev. 04 — 06 January 2004
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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