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PDF P89LPC922FDH Data sheet ( Hoja de datos )

Número de pieza P89LPC922FDH
Descripción 8-bit microcontrollers with two-clock 80C51 core 2 kB/4 kB/8 kB 3 V low-power Flash with 256-byte data RAM
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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P89LPC920/921/922
8-bit microcontrollers with two-clock 80C51 core
2 kB/4 kB/8 kB 3 V low-power Flash with 256-byte data RAM
Rev. 06 — 21 November 2003
Product data
1. General description
The P89LPC920/921/922 are single-chip microcontrollers designed for applications
demanding high-integration, low cost solutions over a wide range of performance
requirements. The P89LPC920/921/922 is based on a high performance processor
architecture that executes instructions in two to four clocks, six times the rate of
standard 80C51 devices. Many system-level functions have been incorporated into
the P89LPC920/921/922 in order to reduce component count, board space, and
system cost.
2. Features
2.1 Principal features
s 2 kB/4 kB/8 kB Flash code memory with 1 kB erasable sectors, 64-byte erasable
page size, and single byte erase.
s 256-byte RAM data memory.
s Two 16-bit counter/timers. Each timer may be configured to toggle a port output
upon timer overflow or to become a PWM output.
s Real-Time clock that can also be used as a system timer.
s Two analog comparators with selectable inputs and reference source.
s Enhanced UART with fractional baud rate generator, break detect, framing error
detection, automatic address detection and versatile interrupt capabilities.
s 400 kHz byte-wide I2C-bus communication port.
s Configurable on-chip oscillator with frequency range and RC oscillator options
(selected by user programmed Flash configuration bits). The RC oscillator option
allows operation without external oscillator components. Oscillator options
support frequencies from 20 kHz to the maximum operating frequency of 12 MHz.
The RC oscillator option is selectable and fine tunable.
s 2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
s 15 I/O pins minimum. Up to 18 I/O pins while using on-chip oscillator and reset
options.
2.2 Additional features
s 20-pin TSSOP and DIP packages.
s A high performance 80C51 CPU provides instruction cycle times of 167 ns to
333 ns for all instructions except multiply and divide when executing at 12 MHz.
This is 6 times the performance of the standard 80C51 running at the same clock
frequency. A lower clock frequency for the same performance results in power
savings and reduced EMI.

1 page




P89LPC922FDH pdf
Philips Semiconductors
5. Pinning information
5.1 Pinning
P89LPC920/921/922
8-bit microcontrollers with two-clock 80C51 core
handbook, halfpage
KBI0/CMP2/P0.0 1
P1.7 2
P1.6 3
RST/P1.5 4
VSS 5
XTAL1/P3.1 6
CLKOUT/XTAL2/P3.0 7
INT1/P1.4 8
SDA/INT0/P1.3 9
SCL/T0/P1.2 10
Fig 2. TSSOP20 pin configuration.
20 P0.1/CIN2B/KBI1
19 P0.2/CIN2A/KBI2
18 P0.3/CIN1B/KBI3
17 P0.4/CIN1A/KBI4
16 P0.5/CMPREF/KBI5
15 VDD
14 P0.6/CMP1/KBI6
13 P0.7/T1/KBI7
12 P1.0/TXD
11 P1.1/RXD
002aaa408
handbook, halfpage
KBI0/CMP2/P0.0 1
P1.7 2
P1.6 3
RST/P1.5 4
VSS 5
XTAL1/P3.1 6
CLKOUT/XTAL2/P3.0 7
INT1/P1.4 8
SDA/INT0/P1.3 9
SCL/T0/P1.2 10
Fig 3. DIP20 pin configuration.
20 P0.1/CIN2B/KBI1
19 P0.2/CIN2A/KBI2
18 P0.3/CIN1B/KBI3
17 P0.4/CIN1A/KBI4
16 P0.5/CMPREF/KBI5
15 VDD
14 P0.6/CMP1/KBI6
13 P0.7/T1/KBI7
12 P1.0/TXD
11 P1.1/RXD
002aaa407
9397 750 12285
Product data
Rev. 06 — 21 November 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
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Table 4: Special function registers…continued
* indicates SFRs that are bit addressable.
Name
Description
SFR Bit functions and addresses
addr. MSB
LSB
Reset value
Hex Binary
I2SCLL
Serial clock generator/SCL
duty cycle register LOW
DCH
00 00000000
I2STAT I2C status register
D9H STA.4 STA.3 STA.2 STA.1 STA.0
0
0
0 F8 11111000
Bit address AF AE AD AC AB AA A9 A8
IEN0*
Interrupt enable 0
A8H EA EWDRT EBO ES/ESR ET1 EX1 ET0 EX0 00[1] 00000000
Bit address EF EE ED EC EB EA E9 E8
IEN1*
Interrupt enable 1
E8H - EST -
-
-
EC
EKBI
EI2C 00[1] 00x00000
Bit address BF BE BD BC BB BA B9 B8
IP0* Interrupt priority 0
B8H - PWDRT PBO PS/PSR PT1 PX1 PT0 PX0 00[1] x0000000
IP0H
Interrupt priority 0 HIGH
B7H
-
PWDRT PBOH
PSH/
PT1H
PX1H
PT0H
PX0H 00[1] x0000000
H PSRH
Bit address FF FE FD FC FB FA F9 F8
IP1* Interrupt priority 1
F8H - PST -
-
-
PC
PKBI
PI2C 00[1] 00x00000
IP1H
Interrupt priority 1 HIGH
F7H -
PSTH
-
-
-
PCH
PKBIH PI2CH 00[1] 00x00000
KBCON Keypad control register
94H -
-
-
-
-
-
PATN
KBIF 00[1] xxxxxx00
_SEL
KBMASK Keypad interrupt mask
register
86H
00 00000000
KBPATN Keypad pattern register
93H
FF 11111111
Bit address 87 86 85 84 83 82 81 80
P0* Port 0
80H T1/KB7 CMP1 CMPREF CIN1A
/KB6
/KB5
/KB4
CIN1B
/KB3
CIN2A
/KB2
CIN2B
/KB1
CMP2
/KB0
[1]
Bit address 97 96 95 94 93 92 91 90
P1* Port 1
90H -
-
RST
INT1
INT0/ T0/SCL RXD
TXD
SDA
[1]
Bit address B7 B6 B5 B4 B3 B2 B1 B0
P3* Port 3
B0H - - - - - - XTAL1 XTAL2
[1]
P0M1
Port 0 output mode 1
84H (P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF
11111111
P0M2
Port 0 output mode 2
85H (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00
00000000
P1M1
Port 1 output mode 1
91H (P1M1.7) (P1M1.6) - (P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3[1] 11x1xx11

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