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PDF P87LPC760 Data sheet ( Hoja de datos )

Número de pieza P87LPC760
Descripción Low power/ low price/ low pin count (14 pin) microcontroller with 1 kbyte OTP
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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No Preview Available ! P87LPC760 Hoja de datos, Descripción, Manual

INTEGRATED CIRCUITS
P87LPC760
Low power, low price, low pin count
(14 pin) microcontroller with 1 kbyte OTP
Preliminary data
IC28 Data Handbook
2002 Mar 07
Philips
Semiconductors

1 page




P87LPC760 pdf
Philips Semiconductors
Low power, low price, low pin count (14 pin)
microcontroller with 1 kbyte OTP
PIN CONFIGURATION, 14-PIN TSSOP AND 14-PIN DIP PACKAGES
P1.7 1
RST/P1.5 2
VSS 3
X1/P2.1 4
X2/CLKOUT/P2.0 5
SDA/INT0/P1.3 6
SCL/T0/P1.2 7
14 P0.3/CIN1B
13 P0.4/CIN1A
12 P0.5/CMPREF
11 VDD
10 P0.6/CMP1
9 P1.0/TxD
8 P1.1/RxD
SU01527
Preliminary data
P87LPC760
LOGIC SYMBOL
CIN1B
CIN1A
CMPREF
CMP1
CLKOUT/X2
X1
VDD
VSS
TxD
RxD
T0/SCL
INT0/SDA
RST
SU01528
2002 Mar 07
2

5 Page





P87LPC760 arduino
Philips Semiconductors
Low power, low price, low pin count (14 pin)
microcontroller with 1 kbyte OTP
Preliminary data
P87LPC760
FUNCTIONAL DESCRIPTION
Details of P87LPC760 functions will be described in the following
sections.
Enhanced CPU
The P87LPC760 uses an enhanced 80C51 CPU which runs at twice
the speed of standard 80C51 devices. This means that the
performance of the P87LPC760 running at 5 MHz is exactly the
same as that of a standard 80C51 running at 10 MHz. A machine
cycle consists of 6 oscillator cycles, and most instructions execute in
6 or 12 clocks. A user configurable option allows restoring standard
80C51 execution timing. In that case, a machine cycle becomes 12
oscillator cycles.
In the following sections, the term “CPU clock” is used to refer to the
clock that controls internal instruction execution. This may
sometimes be different from the externally applied clock, as in the
case where the part is configured for standard 80C51 timing by
means of the CLKR configuration bit or in the case where the clock
is divided down via the setting of the DIVM register. These features
are described in the Oscillator section.
Analog Functions
The P87LPC760 incorporates one Analog Comparator. In order to
give the best analog function performance and to minimize power
consumption, pins that are actually being used for analog functions
must have the digital outputs and the digital inputs disabled.
Digital outputs are disabled by putting the port output into the Input
Only (high impedance) mode as described in the I/O Ports section.
Digital inputs on port 0 may be disabled through the use of the
PT0AD register. Each bit in this register corresponds to one pin of
Port 0. Setting the corresponding bit in PT0AD disables that pin’s
digital input. Port bits that have their digital inputs disabled will be
read as 0 by any instruction that accesses the port.
Analog Comparators
An analog comparator is provided on the P87LPC760. Input and
output options allow use of the comparator in a number of different
configurations. Comparator operation is such that the output is a
logical one (which may be read in a register and/or routed to a pin)
when the positive input (one of two selectable pins) is greater than
the negative input (selectable from a pin or an internal reference
voltage). Otherwise the output is a zero. The comparator may be
configured to cause an interrupt when the output value changes.
Comparator Configuration
The comparator has a control register, CMP1. The control register is
shown in Figure 2.
The overall connections to the comparator are shown in Figure 3.
There are eight possible configurations for the comparator, as
determined by the control bits in the CMP1 register: CP1, CN1, and
OE1. These configurations are shown in Figure 4. The comparator
functions down to a VDD of 3.0V.
When the comparator is first enabled, the comparator output and
interrupt flag are not guaranteed to be stable for 10 microseconds.
The comparator interrupt should not be enabled during that time,
and the comparator interrupt flag must be cleared before the
interrupt is enabled in order to prevent an immediate interrupt
service.
CMP1
Address: ACh
Not Bit Addressable
Reset Value: 00h
76543210
— — CE1 CP1 CN1 OE1 CO1 CMF1
BIT SYMBOL
CMP1.7, 6
CMP1.5
CE1
CMP1.4
CP1
CMP1.3
CN1
CMP1.2
CMP1.1
CMP1.0
OE1
CO1
CMF1
FUNCTION
Reserved for future use. Should not be set to 1 by user programs.
Comparator enable. When set by software, the corresponding comparator function is enabled.
Comparator output is stable 10 microseconds after CE1 is first set.
Comparator positive input select. When 0, CIN1A is selected as the positive comparator input. When
1, CIN1B is selected as the positive comparator input.
Comparator negative input select. When 0, the comparator reference pin CMPREF is selected as
the negative comparator input. When 1, the internal comparator reference Vref is selected as the
negative comparator input.
Output enable. When 1, the comparator output is connected to the CMP1 pin if the comparator is
enabled (CE1 = 1). This output is asynchronous to the CPU clock.
Comparator output, synchronized to the CPU clock to allow reading by software. Cleared when the
comparator is disabled (CE1 = 0).
Comparator interrupt flag. This bit is set by hardware whenever the comparator output CO1 changes
state. This bit will cause a hardware interrupt if enabled and of sufficient priority. Cleared by
software and when the comparator is disabled (CE1 = 0).
SU01531
Figure 2. Comparator Control Register (CMP1)
2002 Mar 07
8

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