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Número de pieza P87C749EBPN
Descripción 80C51 8-bit microcontroller family 2K/64 OTP/ROM/ 5 channel 8-bit A/D/ PWM/ low pin count
Fabricantes NXP Semiconductors 
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INTEGRATED CIRCUITS
83C749/87C749
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM,
low pin count
Preliminary specification
Supersedes data of 1998 Jan 06
IC20 Data Handbook
1998 Apr 23
Philips
Semiconductors

1 page




P87C749EBPN pdf
Philips Semiconductors
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
Preliminary specification
83C749/87C749
PIN DESCRIPTION
MNEMONIC PIN NO. TYPE
NAME AND FUNCTION
VSS
VCC
P0.0–P0.4
12
28
8–6
23, 24
I Circuit Ground Potential.
I Supply voltage during normal, idle, and power-down operation.
I/O Port 0: Port 0 is a 5-bit bidirectional port. Port 0.0–P0.2 are open drain. Port 0.0–P0.2 pins that have
1s written to them float, and in that state can be used as high-impedance inputs. P0.3–P0.4 are
bidirectional I/O port pins with internal pull-ups. These pins are driven low if the port register bit is
written with a 0. The state of the pin can always be read from the port register by the program. Port 0.3
and 0.4 have internal pull-ups that function identically to port 3. Pins that have 1s written to them are
pulled high by the internal pull-ups and can be used as inputs.
While P0.0 anbd P0.1 differ from “standard TTL” characteristics, they are close enough for the pins to
still be used as general-purpose I/O.
6 I VPP (P0.2) – Programming voltage input. (See Note 2.)
7 I OE/PGM (P0.1) – Input which specifies verify mode (output enable) or the program mode.
OE/PGM = 1 output enabled (verify mode).
OE/PGM = 0 program mode.
8 I ASEL (P0.0) – Input which indicates which bits of the EPROM address are applied to port 3.
ASEL = 0 low address byte available on port 3.
ASEL = 1 high address byte available on port 3 (only the three least significant bits are used).
P1.0–P1.7
13–17,
20–22
20
21
22
13–17
I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to
them are pulled high by the internal pull-ups and can be used as inputs. P0.3–P0.4 pins are
bidirectional I/O port pins with internal pull-ups. As inputs, port 1 pins that are externally pulled low will
source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 1 also
serves the special function features of the SC80C51 family as listed below:
I INT0 (P1.5): External interrupt.
I INT1 (P1.6): External interrupt.
I T0 (P1.7): Timer 0 external input.
I ADC0 (P1.0)–ADC4 (P1.4): Port 1 also functions as the inputs to the five channel multiplexed A/D
converter. These pins can be used as outputs only if the A/D function has been disabled. These pins
can be used as digital inputs while the A/D converter is enabled.
Port 1 serves to output the addressed EPROM contents in the verify mode and accepts as inputs the
value to program into the selected address during the program mode.
P3.0–P3.7
5–1,
27–25
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to
them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are
externally being pulled low will source current because of the pull-ups. (See DC Electrical
Characteristics: IIL). Port 3 also functions as the address input for the EPROM memory location to be
programmed (or verified). The 11-bit address is multiplexed into this port as specified by P0.0/ASEL.
RST
9 I Reset: A high on this pin for two machine cycles while the oscillator is running resets the device. An
internal diffused resistor to VSS permits a power-on RESET using only an external capacitor to VCC.
After the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places the device
in the programming state allowing programming address, data and VPP to be applied for programming
or verification purposes. The RESET serial sequence must be synchronized with the X1 input.
X1 11 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. X1
also serves as the clock to strobe in a serial bit stream into RESET to place the device in the
programming state.
X2 10 O Crystal 2: Output from the inverting oscillator amplifier.
AVCC 1
19 I Analog supply voltage and reference input.
AVSS 1
18 I Analog supply and reference ground.
NOTE:
1. AVSS (reference ground) must be connected to 0V (ground). AVCC (reference input) cannot differ from VCC by more than ±0.2V, and must be
in the range 4.5V to 5.5V.
2. When P0.2 is at or close to 0 volt, it may affect the internal ROM operation. We recommend that P0.2 be tied to VCC via a small pullup
(e.g., 2k).
1998 Apr 23
5

5 Page





P87C749EBPN arduino
Philips Semiconductors
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
Preliminary specification
83C749/87C749
COUNTER/TIMER
The 8XC749 counter/timer is designated Timer 0 and is separate
from Timer I and from the PWM. Its operation is similar to mode 2 of
the 80C51 counter/timer, extended to 16 bits. When Timer 0 is used
in the external counter mode, the T0 input (P1.7) is sampled every
S4P1. The counter/timer function is controlled using the timer control
register (TCON).
TCON Register
MSB
LSB
GATE
C/T
TF
TR
IE0 IT0 IE1
IT1
Position Symbol
Function
TCON.7 GATE 1 – Timer 0 is enabled only when INT0 pin is
high and TR is 1.
0 – Timer 0 is enabled only when TR is 1.
TCON.6 C/T 1 – Counter operation from T0 pin.
0 – Timer operation from internal clock.
TCON.5 TF 1 – Set on overflow of T0.
0 – Cleared when processor vectors to interrupt
routine and by reset.
TCON.4 TR 1 – Enable timer 0
0 – Disable timer 0
TCON.3 IE0 1 – Edge detected on INT0
TCON.2 IT0 1 – INT0 is edge triggered.
0 – INT0 is level sensitive.
TCON.1 IE1 1 – Edge detected on INT1
TCON.0 IT1 1 – INT1 is edge triggered.
0 – INT1 is level sensitive.
These flags are functionally identical to the corresponding 80C51
flags except that there is only one of the 80C51 style timers, and the
flags are combined into one register.
Note that the positions of the IE0/IT0 and IE1/IT1 bits are
transposed from the positions used in the standard 80C51 TCON
register.
Timer I may be used as a fixed time base timer or watchdog timer.
Timer T0 is a 16-bit autoreloadable timer/counter, that operates
similar to mode 2 operation on the 80C51, but is extended to 16 bits.
The timer/counter is clocked by either 1/12 the oscillator frequency
or by transitions on the T0 pin. The C/T bit in special function
register TCON selects between these two modes. When the TCON
TR bit is set, the timer/counter is enabled. Register pair TH and TL
are incremented by the clock source. When the register pair
overflows, the register pair is reloaded with the values in registers
RTH and RTL. The value in the reload registers is left unchanged.
The TF bit in special function register TCON is set on counter
overflow and, if the interrupt is enabled, will generate an interrupt
(see Figure 3).
OSC
T0 Pin
TR
Gate
INT0 Pin
÷ 12
C/T = 0
C/T = 1
TL TH
Reload
RTL RTH
Figure 3. 83C749 Counter/Timer Block Diagram
ABSOLUTE MAXIMUM RATINGS1, 3, 4
PARAMETER
Storage temperature range
Voltage from VCC to VSS
Voltage from any pin to VSS (except VPP)
Power dissipation
Voltage from VPP pin to VSS
NOTES ON PAGE 13.
RATING
–65 to +150
–0.5 to +6.5
–0.5 to VCC + 0.5
1.0
–0.5 to + 13.0
TF
Int.
SU00300
UNIT
°C
V
V
W
V
1998 Apr 23
11

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