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PDF P87C748EBAA Data sheet ( Hoja de datos )
| Número de pieza | P87C748EBAA | |
| Descripción | 80C51 8-bit microcontroller family 2K/64 OTP/ROM/ low pin count | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
83C748/87C748
80C51 8-bit microcontroller family
2K/64 OTP/ROM, low pin count
Preliminary specification
Supersedes data of 1998 Apr 23
IC20 Data Handbook
1999 Apr 15
Philips
Semiconductors
1 page  
Philips Semiconductors
80C51 8-bit microcontroller family
2K/64 OTP/ROM, low pin count
Preliminary specification
83C748/87C748
DC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C, VCC = 5V ±10%, VSS = 0V1
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
MIN MAX
UNIT
VIL
VIH
VIH1
VIL1
VIH2
VOL
VOL1
VOH
Input low voltage
Input high voltage, except X1, RST
Input high voltage, X1, RST
P0.2
Input low voltage
Input high voltage
Output low voltage, ports 1 and 3
Output low voltage, port 0.2
Output high voltage, ports 1 and 3
IOL = 1.6mA2
IOL = 3.2mA2
IOH = –60µA
IOH = –25µA
IOH = –10µA
–0.5
0.2VCC+0.9
0.7VCC
0.2VDD–0.1
VCC+0.5
VCC+0.5
–0.5
0.7VCC
2.4
0.75VCC
0.9VCC
0.3VCC
VCC+0.5
0.45
0.45
V
V
V
V
V
V
V
V
V
V
VOL2
C
Port 0.0 and 0.1 – Drivers
Output low voltage
Driver, receiver combined:
Capacitance
IOL = 3mA
(over VCC range)
0.4 V
10 pF
IIL
ITL
ILI
RRST
CIO
IPD
VPP
Logical 0 input current, ports 1 and 3
Logical 1 to 0 transition current, ports 1 and 33
Input leakage current, port 0
Internal pull-down resistor
Pin capacitance
Power-down current4
VPP program voltage (for 87C748 only)
VIN = 0.45V
VIN = 2V (0 to 70°C)
0.45 < VIN < VCC
Test freq = 1MHz,
Tamb = 25°C
VCC = 2 to VCC max
VSS = 0V
VCC = 5V±10%
Tamb = 21°C to 27°C
25
12.5
–50
–650
±10
175
10
50
13.0
µA
µA
µA
kΩ
pF
µA
V
IPP Program current (for 87C748 only)
VPP = 13.0V
50 mA
ICC Supply current (see Figure 2)
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise
noted.
2. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:
10mA
Maximum IOL per 8-bit port:
26mA
Maximum total IOL for all outputs:
67mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
3. Pins of ports 1 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when VIN is approximately 2V.
4. Power-down ICC is measured with all output pins disconnected; port 0 = VCC; X2, X1 n.c.; RST = VSS.
5. Active ICC is measured with all output pins disconnected; X1 driven with tCLCH, tCHCL = 5ns, VIL = VSS + 0.5V, VIH = VCC – 0.5V; X2 n.c.;
RST = port 0 = VCC. ICC will be slightly higher if a crystal oscillator is used.
6. Idle ICC is measured with all output pins disconnected; X1 driven with tCLCH, tCHCL = 5ns, VIL = VSS + 0.5V, VIH = VCC – 0.5V; X2 n.c.;
port 0 = VCC; RST = VSS.
1999 Apr 15
5
5 Page 
Philips Semiconductors
80C51 8-bit microcontroller family
2K/64 OTP/ROM, low pin count
Preliminary specification
83C748/87C748
87C748 PROGRAMMING CONSIDERATIONS
EPROM Characteristics
The 87C748 is programmed by using a modified Quick-Pulse
Programming algorithm similar to that used for devices such as the
87C451 and 87C51. It differs from these devices in that a serial data
stream is used to place the 87C748 in the programming mode.
Figure 5 shows a block diagram of the programming configuration
for the 87C748. Port pin P0.2 is used as the programming voltage
supply input (VPP signal). Port pin P0.1 is used as the program
(PGM/) signal. This pin is used for the 25 programming pulses.
Port 3 is used as the address input for the byte to be programmed
and accepts both the high and low components of the eleven bit
address. Multiplexing of these address components is performed
using the ASEL input. The user should drive the ASEL input high
and then drive port 3 with the high order bits of the address. ASEL
should remain high for at least 13 clock cycles. ASEL may then be
driven low which latches the high order bits of the address internally.
the high address should remain on port 3 for at least two clock
cycles after ASEL is driven low. Port 3 may then be driven with the
low byte of the address. The low address will be internally stable 13
clock cycles later. The address will remain stable provided that the
low byte placed on port 3 is held stable and ASEL is kept low. Note:
ASEL needs to be pulsed high only to change the high byte of the
address.
Port 1 is used as a bidirectional data bus during programming and
verify operations. During programming mode, it accepts the byte to
be programmed. During verify mode, it provides the contents of the
EPROM location specified by the address which has been supplied
to Port 3.
The XTAL1 pin is the oscillator input and receives the master system
clock. This clock should be between 1.2 and 6MHz.
The RESET pin is used to accept the serial data stream that places
the 87C748 into various programming modes. This pattern consists
of a 10-bit code with the LSB sent first. Each bit is synchronized to
the clock input, X1.
Programming Operation
Figures 6 and 7 show the timing diagrams for the program/verify
cycle. RESET should initially be held high for at least two machine
cycles. P0.1 (PGM/) and P0.2 (VPP) will be at VOH as a result of the
RESET operation. At this point, these pins function as normal
quasi-bidirectional I/O ports and the programming equipment may
pull these lines low. However, prior to sending the 10-bit code on the
RESET pin, the programming equipment should drive these pins
high (VIH). The RESET pin may now be used as the serial data input
for the data stream which places the 87C748 in the programming
mode. Data bits are sampled during the clock high time and thus
should only change during the time that the clock is low. Following
transmission of the last data bit, the RESET pin should be held low.
Next the address information for the location to be programmed is
placed on port 3 and ASEL is used to perform the address
multiplexing, as previously described. At this time, port 1 functions
as an output.
A high voltage VPP level is then applied to the VPP input (P0.2).
(This sets Port 1 as an input port). The data to be programmed into
the EPROM array is then placed on Port 1. This is followed by a
series of programming pulses applied to the PGM/ pin (P0.1). These
pulses are created by driving P0.1 low and then high. This pulse is
repeated until a total of 25 programming pulses have occurred. At
the conclusion of the last pulse, the PGM/ signal should remain high.
The VPP signal may now be driven to the VOH level, placing the
87C748 in the verify mode. (Port 1 is now used as an output port).
After four machine cycles (48 clock periods), the contents of the
addressed location in the EPROM array will appear on Port 1.
The next programming cycle may now be initiated by placing the
address information at the inputs of the multiplexed buffers, driving
the VPP pin to the VPP voltage level, providing the byte to be
programmed to Port1 and issuing the 26 programming pulses on the
PGM/ pin, bringing VPP back down to the VC level and verifying the
byte.
Programming Modes
The 87C748 has four programming features incorporated within its
EPROM array. These include the USER EPROM for storage of the
application’s code, a 16-byte encryption key array and two security
bits. Programming and verification of these four elements are
selected by a combination of the serial data stream applied to the
RESET pin and the voltage levels applied to port pins P0.1 and
P0.2. The various combinations are shown in Table 3.
Table 3. Implementing Program/Verify Modes
OPERATION
SERIAL
CODE
P0.1
(PGM/)
P0.2
(VPP)
Program user EPROM
296H
–*
Verify user EPROM
Program key EPROM
296H
292H
VIH
–*
Verify key EPROM
Program security bit 1
292H
29AH
VIH
–*
Program security bit 2
298H
–*
Verify security bits
29AH
VIH
NOTE:
* Pulsed from VIH to VIL and returned to VIH.
VPP
VIH
VPP
VIH
VPP
VPP
VIH
Encryption Key Table
The 87C748 includes a 16-byte EPROM array that is programmable
by the end user. The contents of this array can then be used to
encrypt the program memory contents during a program memory
verify operation. When a program memory verify operation is
performed, the contents of the program memory location is
XNOR’ed with one of the bytes in the 16-byte encryption table. The
resulting data pattern is then provided to port 1 as the verify data.
The encryption mechanism can be disable, in essence, by leaving
the bytes in the encryption table in their erased state (FFH) since
the XNOR product of a bit with a logical one will result in the original
bit. The encryption bytes are mapped with the code memory in
16-byte groups. the first byte in code memory will be encrypted with
the first byte in the encryption table; the second byte in code
memory will be encrypted with the second byte in the encryption
table and so forth up to and including the 16the byte. The encryption
repeats in 16-byte groups; the 17th byte in the code memory will be
encrypted with the first byte in the encryption table, and so forth.
1999 Apr 15
11
11 Page | ||
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| PDF Descargar | [ Datasheet P87C748EBAA.PDF ] | |
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