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PDF P83C770 Data sheet ( Hoja de datos )

Número de pieza P83C770
Descripción Microcontrollers for NTSC TVs with On-Screen Display OSD and Closed Caption CC
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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No Preview Available ! P83C770 Hoja de datos, Descripción, Manual

INTEGRATED CIRCUITS
DATA SHEET
P8xCx70 family
Microcontrollers for NTSC TVs with
On-Screen Display (OSD) and
Closed Caption (CC)
Product specification
Supersedes data of 1999 May 17
File under Integrated Circuits, IC20
1999 Jun 11

1 page




P83C770 pdf
Philips Semiconductors
Microcontrollers for NTSC TVs with On-Screen
Display (OSD) and Closed Caption (CC)
5 PINNING INFORMATION
5.1 Pinning
Product specification
P8xCx70 family
1999 Jun 11
handbook, halfpage
P0.0/PWM8 1
52 P3.7
P0.1/PWM7 2
51 P3.6
P0.2/PWM6 3
50 P3.5/SDA
P0.3/PWM5 4
49 P3.4/SCL
P0.4/PWM4 5
48 P3.3/T1
P0.5/PWM3 6
47 P3.2/INT0
P0.6/PWM2 7
46 P3.1/T0
P0.7/PWM1 8
45 P3.0/INT1
P1.0/AFT0 9
P1.1/AFT1 10
44 VDDC
43 RESET
P1.2/AFT2 11
42 XI
P1.3/PWM0 12
VSSD 13
P2.7 14
P2.6 15
P2.5 16
P83C270
P83C370
P83C570
P83C770
P87C770
41 XO
40 VSSD
39 VDDP
38 VDDA
37 VSYNC
P2.4 17
36 HSYNC
P2.3 18
35 FB
P2.2 19
34 R
P2.1 20
33 G
P2.0 21
32 B
VSSA 22
CVBS 23
31 REFH
30 P1.4
STN 24
29 ALE/PROG
BLK 25
IREF 26
28 VPP/EA
27 PSEN
MGR372
Fig.2 Pinning configuration.
5

5 Page





P83C770 arduino
Philips Semiconductors
Microcontrollers for NTSC TVs with On-Screen
Display (OSD) and Closed Caption (CC)
Product specification
P8xCx70 family
8 WATCHDOG TIMER (T3)
In addition to the standard timers, an 8-bit Watchdog Timer
is also incorporated. When a timer overflow occurs, the
microcontroller is reset. To prevent a system reset the
timer must be reloaded in time by the application software.
If the processor suffers a hardware/software malfunction,
the software will fail to reload the timer. This failure will
result in a reset upon overflow thus preventing the
processor running out of control.
The timer is incremented every 2 ms. The timer interval
between the timer reloading and the occurrence of a reset
depends on the reloaded value. This may range from
2 to 512 ms according to the following formula:
Ttimer = ( 256 T3 value) × 2 ms
The Watchdog Timer can only be reloaded if the condition
flag WLE in SFR PCON has been previously set HIGH by
software. At the moment the counter is loaded WLE is
automatically cleared.
The Watchdog Timer is controlled by the EW bit in SFR
BWC (see Section 11.5). If EW = 1, the Watchdog Timer is
enabled and the Power-down mode disabled. If EW = 0,
the Watchdog Timer is disabled and the Power-down
mode enabled.
In the Idle mode the Watchdog Timer and reset circuitry
remain active.
8.1 Watchdog Timer Register (WDT)
Table 4 Watchdog Timer Register (SFR address FFH)
76543210
D7 D6 D5 D4 D3 D2 D1 D0
Table 5 Description of the T3 bits
BIT
7 to 0
SYMBOL
D7 to D0
DESCRIPTION
Watchdog Timer reload value. These 8 bits determine the timer interval. If WDT holds
FFH the timer interval is 2 ms. If WDT holds 00H the timer interval is 512 ms.
handbook, full pagewidth
INTERNAL BUS
1/12 fosc
write T3
1999 Jun 11
PRESCALER
11-BIT
CLEAR
WDT REGISTER
(8-BIT)
LOAD LOADEN
internal reset
RESET
RRESET
CLEAR
WLE
PCON.4
IDL
LOADEN
PCON.0
INTERNAL BUS
Fig.4 Watchdog Timer block diagram.
11
MGL298

11 Page







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