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PDF P83C652EFBB Datasheet ( Hoja de datos )

Número de pieza P83C652EFBB
Descripción CMOS single-chip 8-bit microcontrollers
Fabricantes NXP 
Logotipo NXP Logotipo

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P83C652EFBB Hoja de datos, Descripción, Manual
INTEGRATED CIRCUITS
80C652/83C652
CMOS single-chip 8-bit microcontrollers
Product specification
Supersedes data of 1996 Aug 15
IC20 Data Handbook
1997 Dec 05
Philips
Semiconductors

1 page

P83C652EFBB pdf
Phlips Semiconductors
CMOS single-chip 8-bit microcontrollers
BLOCK DIAGRAM
FREQUENCY
REFERENCE
XTAL2 XTAL1
OSCILLATOR
AND
TIMING
PROGRAM
MEMORY
(8K x 8 ROM)
DATA
MEMORY
(256 x 8 RAM)
COUNTERS
T0 T1
TWO 16-BIT
TIMER/EVENT
COUNTERS
Product specification
80C652/83C652
CPU
I2C SERIAL I/O
SDA SHARED
WITH
SCL PORT 1
INTERNAL
INTERRUPTS
64K BYTE BUS
EXPANSION
CONTRTOL
PROGRAMMABLE I/O
PROG SERIAL PORT
FULL DUPLEX UART
SYNCHRONOUS SHIFT
INT0
INT1
EXTERNAL
INTERRUPTS
CONTROL
PARALLEL PORTS,
ADDRESS/DATA BUS
AND I/O PINS
SERIAL IN SERIAL OUT
SHARED WITH
PORT 3
1997 Dec 05
5

5 Page

P83C652EFBB arduino
Phlips Semiconductors
CMOS single-chip 8-bit microcontrollers
Product specification
80C652/83C652
NOTES FOR DC ELECTRICAL CHARACTERISTICS:
1. See Figures 9 through 11 for IDD test conditions.
2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5ns;
VIL = VSS + 0.5V; VIH = VDD –0.5V; XTAL2 not connected; EA = RST = Port 0 = P1.6 = P1.7 = VDD. See Figure 9.
3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5ns; VIL = VSS + 0.5V;
VIH = VDD –0.5V; XTAL2 not connected; Port 0 = P1.6 = P1.7 = VDD; EA = RST = VSS. See Figure 10.
4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = P1.6 = P1.7 = VDD;
EA = RST = VSS. See Figure 11.
5. 2V VPD VDDmax.
6. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I2C specification, so an input voltage below 0.3VDD will be recognized as a
logic 0 while an input voltage above 0.7VDD will be recognized as a logic 1.
7. Pins of ports 1 , 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when VIN is approximately 2V.
8. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
9. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL = 10mA per port pin; Maximum
IOL = 26mA total for Port 0; Maximum IOL = 15mA total for Ports 1, 2, and 3; Maximum IOL = 71mA total for all output pins. If IOL exceeds the
test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
10. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VDD specification when the
address bits are stabilizing.
11. IDDMAX for other frequencies can be derived from Figure 1, where FREQ is the external oscillator frequency in MHz. IDDMAX is given in mA.
40
IDD
(mA)
30
20
50
IDD
(mA)
40
30
(1)
20
(1)
10
10
(2)
(2)
0
0 4 8 12 16
fXTAL1 (MHz)
(1) MAXIMUM OPERATING MODE: VDD = VDDmax
(2) MAXIMUM IDLE MODE: VDD = VDDmax
These values are valid within the specified
frequency range.
0
04
8 12
(1) MAXIMUM OPERATING MODE: VDD = VDDmax
(2) MAXIMUM IDLE MODE: VDD = VDDmax
These values are valid within the specified
frequency range.
16 24
fXTAL1 (MHz)
Figure 1. IDD vs. Frequency
1997 Dec 05
11

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