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PDF P82B715 Data sheet ( Hoja de datos )
| Número de pieza | P82B715 | |
| Descripción | I2C bus extender | |
| Fabricantes | NXP Semiconductors | |
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P82B715
I2C-bus extender
Rev. 08 — 9 November 2009
Product data sheet
1. General description
The P82B715 is a bipolar IC intended for application in I2C-bus and derivative bus
systems. While retaining all the operating modes and features of the I2C-bus it permits
extension of the practical separation distance between components on the I2C-bus by
buffering both the data (SDA) and the clock (SCL) lines.
The I2C-bus capacitance limit of 400 pF restricts practical communication distances to a
few meters. Using one P82B715 at each end of a long cable (connecting Lx/Ly to Lx/Ly)
reduces that cable’s loading on the linked I2C-buses by a factor of 10 and allows the total
system capacitance load (all devices, cable, connectors, and traces or wires connected to
the I2C-bus) to be around 3000 pF while the loading on each I2C-bus on the Sx/Sy sides
remains below 400 pF. Longer cables or low-cost, general-purpose wiring may be used to
link I2C-bus based modules without degrading noise margins. Multiple P82B715s can be
connected together, linking their Lx/Ly ports, in a star or multi-point architecture as long as
the total capacitance of the system is less than about 3000 pF and each bus at an Sx/Sy
connection is well below 400 pF. This configuration, with the master and/or slave devices
attached to the Sx/Sy port of each P82B715, has full multi-master communication
capability. The P82B715 alone does not support voltage level translation, but it can be
simply implemented using low cost transistors when required. There is no restriction on
interconnecting the Sx/Sy I/Os, and, because the device output levels are always held
within 100 mV of input drive levels, P82B715 is compatible with bus buffers that use
voltage level offsets, e.g., PCA9511A, PCA9517, Sx/Sy side of P82B96.
The lower VOL level and ability to operate with any master, slave or bus buffer is the
primary advantage of the using the P82B715 for long distance buses at the disadvantage
of not isolating bus capacitance like the P82B96 or PCA9600 are able to do. The primary
disadvantage of the P82B96 and PCA9600 is that the static level offset needed to isolate
bus capacitance does not allow these devices to operate with other bus buffers with
special offset levels or with master/slaves that require a VIL lower than 0.8 V with noise
margin. A proven quick design-in point-to-point/multi-point circuit (Figure 9) is included in
Section 8.2 to allow rapid use of the P82B715 along with comparison waveforms so that
the designer can clearly see the trade-offs between the P82B715 and the
P82B96/PCA9600 and choose the type of device that is best for their application.
2. Features
I Dual, bidirectional, unity voltage gain buffer with no external directional control
required
I Compatible with I2C-bus and its derivatives SMBus, PMBus, DDC, etc.
I Logic signal levels may include (but not exceed) both supply and ground
I Logic signal input voltage levels are output without change and are independent of VCC
I ×10 impedance transformation, but does not change logic voltage levels
1 page  
NXP Semiconductors
P82B715
I2C-bus extender
7.2 Lx, Ly: buffered bus LDA or LCL
On the special low-impedance or buffered line side, the corresponding output at the Lx or
Ly pins becomes the LDA data line or LCL clock line.
7.3 VCC, GND: positive and negative supply pins
The power supply voltages at each P82B715 used in a system are normally nominally the
same. If they differ by a significant amount, noise margin may be sacrificed as the bus
HIGH level should not exceed the lowest of those supplies.
8. Application design-in information
By using two (or more) P82B715 ICs, a sub-system can be built that retains the interface
characteristics of a normal I2C-bus device so that the sub-system may be included in, or
added onto, any I2C-bus or related system.
The sub-system shown in Figure 5 features a low-impedance or buffered bus, capable of
driving large wiring capacitance.
The P82B715 will operate with a supply voltage from 3 V to 12.5 V but the logic signal
levels at Sx/Lx are independent of the chip’s supply. They remain at the levels presented
to the chip by the attached ICs. The maximum static I2C-bus sink current, 3 mA, flowing in
either direction in the internal current sense resistor, causes a difference, or offset voltage,
less than 100 mV between the bus logic LOW levels at Sx and Lx. This makes P82B715
fully compatible with all logic signal drivers, including TTL. The P82B715 cannot modify
the bus logic signal voltage levels but it contains internal diodes connected between Lx/Sx
and VCC that will conduct and limit the logic signal swing if the applied logic levels would
have exceeded the supply voltage by more than 0.7 V. In normal applications external
pull-up resistors will pull the connected buses up to the desired voltage HIGH level.
Usually this will be the chip supply, VCC, but for very low logic voltages it is necessary to
use a VCC of at least 3.3 V and preferably even higher. Note that full performance over
temperature is only guaranteed from 4.5 V. Specification de-ratings apply when its supply
voltage is reduced below 4.5 V. The absolute minimum VCC is 3 V.
SDA
P82B715
VCC
1/2
VCC
SCL
1/2
VCC
P82B715
LDA
long
cable
VCC
1/2
LCL
1/2
SDA
I2C-BUS
DEVICE
SCL
standard
I2C-bus
special
buffered bus
special
buffered bus
Fig 5. Minimum sub-system with P82B715
standard
I2C-bus
002aad690
P82B715_8
Product data sheet
Rev. 08 — 9 November 2009
© NXP B.V. 2009. All rights reserved.
5 of 23
5 Page 
NXP Semiconductors
P82B715
I2C-bus extender
• The 300 ns bus fall time, and the Standard-mode I2C-bus limit specification limit of
400 pF, must also be observed. If the 400 pF limit is observed the fall time limit will be
met. Allocate about 1⁄3 of this 400 pF limit, or 133 pF, to each I2C-bus leaving 2⁄3, or
266 pF, for the cable bus loading as it will appear at the Sx/Sy pins. The ×10 gain of
P82B715 allows the loading at Lx/Ly to be 10 times the load at Sx/Sy, so 2660 pF
maximum. The loading at Lx/Ly due to the other standard buses is 133 pF each. For
just one remote module the cable capacitance may then be up to
(2660 − 133) = 2530 pF. For typical twisted pair or flat cables, as used for telephony or
Ethernet (Cat5e) wiring, that capacitance is around 50 pF to 70 pF / meter so the
cable could, in theory, be up to 50 m long. From practical experience, 30 m has
proven a safe cable length to be driven in this simple way, up to 100 kHz, with the
values shown. Longer distances and higher speeds are possible but require more
careful design.
• If there are severe EMI/ESD tests to be passed then large clamp diodes can be fitted
on the cable bus at each module to VCC and to ground. They may be diodes rated for
this ESD application, or simply large rectifiers (1N4000). The low-impedance bus
easily accommodates their relatively large capacitance. The P82B715 does not
provide any isolation between Lx and Sx, so this clamping method provides the best
protection for the lower voltage I2C-bus parts. The VCC supply should be bypassed
using low-impedance capacitors. Zeners may be fitted to prevent the supply rising due
to rectification during very large interference.
8.3 Comparison of P82B715 versus P82B96 in the quick design-in
point-to-point/multi-point circuit
The lower VOL level and ability to operate with any master, slave or bus buffer is the
primary advantage of the using the P82B715 for long distance buses at the disadvantage
of not isolating bus capacitance like the P82B96 or PCA9600 are able to do. The primary
disadvantage of the P82B96 and PCA9600 is that the static level offset needed to isolate
bus capacitance does not allow these devices to operate with other bus buffers with
special offset levels or with master/slaves that require a VIL lower than 0.8 V with noise
margin. Waveforms using the circuit shown in Figure 9 are shown in Figure 10 using the
P82B715 and Figure 11 using the P82B96 so that the designer can clearly see these
trade-offs and choose the type of device that is best for their application.
P82B715_8
Product data sheet
7
voltage
(V)
5
3
SDA
1
SCL
−1
0
4
SDA
SCL
8
12
002aad818
SCL
SDA
16 20
time (µs)
Fig 10. Clock and data signal output at Sx/Sy from a system with P82B715 at each end of
a 20 m cable
Rev. 08 — 9 November 2009
© NXP B.V. 2009. All rights reserved.
11 of 23
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