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Número de pieza P80C851IBB
Descripción CMOS single-chip 8-bit microcontroller with on-chip EEPROM
Fabricantes NXP 
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P80C851IBB Hoja de datos, Descripción, Manual
INTEGRATED CIRCUITS
80C851/83C851
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
Product specification
Supersedes data of 1992 Nov 25
IC20 Data Handbook
1998 Jul 03
Philips
Semiconductors

1 page

P80C851IBB pdf
Philips Semiconductors
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
Product specification
80C851/83C851
PIN DESCRIPTION
PIN NO.
MNEMONIC DIP LCC QFP TYPE
NAME AND FUNCTION
VSS 20 22 16, 39 I Ground: 0V reference.
VDD
40 44 38
I Power Supply: This is the power supply voltage for normal, idle, and power-down
operation.
P0.0–0.7
39–32 43–36 37–30
I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory.
In this application, it uses strong internal pull-ups when emitting 1s.
P1.0–P1.7
P2.0–P2.7
1–8 2–9 40–44, I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have
1–3 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 1 pins that are externally pulled low will source current because of the
internal pull-ups. (See DC Electrical Characteristics: IIL).
21–28 24–31 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have
1s written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 2 pins that are externally being pulled low will source current because of the
internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order
address byte during fetches from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it
uses strong internal pull-ups when emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function
register.
P3.0–P3.7
RST
ALE
10–17 11,
5,
13–19 7–13
10 11
5
11 13
7
12 14
8
13 15
9
14 16 10
15 17 11
16 18 12
17 19 13
9 10 4
30 33 27
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have
1s written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 3 pins that are externally being pulled low will source current because of the
pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features
of the SC80C51 family, as listed below:
I RxD (P3.0): Serial input port
O TxD (P3.1): Serial output port
I INT0 (P3.2): External interrupt
I INT1 (P3.3): External interrupt
I T0 (P3.4): Timer 0 external input
I T1 (P3.5): Timer 1 external input
O WR (P3.6): External data memory write strobe
O RD (P3.7): External data memory read strobe
I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to VSS permits a power-on reset using only an
external capacitor to VDD.
I/O Address Latch Enable: Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency, and can be used for external timing or clocking. Note that one
ALE pulse is skipped during each access to external data memory.
PSEN
29 32 26
O Program Store Enable: The read strobe to external program memory. When the device
is executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access to
external data memory. PSEN is not activated during fetches from internal program
memory.
EA
31 35 29
I External Access Enable: If during a RESET, EA is held at TTL, level HIGH, the CPU
executes out of the internal program memory ROM provided the Program Counter is less
than 4096. If during a RESET, EA is held a TTL LOW level, the CPU executes out of
external program memory. EA is not allowed to float.
XTAL1
19 21 15
I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
XTAL2
18 20 14
O Crystal 2: Output from the inverting oscillator amplifier.
1998 Jul 03
5

5 Page

P80C851IBB arduino
Philips Semiconductors
CMOS single-chip 8-bit microcontroller
with on-chip EEPROM
Product specification
80C851/83C851
DC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C (VDD = 5V ±10%), –40°C to +85°C (VDD = 5V ±10%), or –40°C to +125°C (VDD = 5V ±10%), VSS = 0V
PART
TEST
LIMITS
SYMBOL
PARAMETER
TYPE
CONDITIONS
MIN
MAX
UNIT
VIL
VIL1
VIH
VIH1
VOL
VOL1
VOH
VOH1
IIL
Input low voltage, except EA
Input low voltage to EA
Input high voltage, except XTAL1, RST
Input high voltage, XTAL1, RST
Output low voltage, ports 1, 2, 3 6
Output low voltage, port 0, ALE, PSEN 6
Output high voltage, ports 1, 2, 3, ALE, PSEN
0 to +70°C
–40 to +85°C
–40 to +125°C
0 to +70°C
–40 to +85°C
–40 to +125°C
0 to +70°C
–40 to +85°C
–40 to +125°C
0 to +70°C
–40 to +85°C
–40 to +125°C
Output high voltage, port 0 in external bus
mode5
Logical 0 input current, ports 1, 2, 3
0 to +70°C
–40 to +85°C
–40 to +125°C
IOL = 1.6mA4
IOL = 3.2mA4
IOH = –60µA,
IOH = –25µA,
IOH = –10µA
IOH = –800µA,
IOH = –300µA,
IOH = –80µA
VIN = 0.45V
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
0.2VDD+0.9
0.2VDD+1.0
0.2VDD+1.0
0.7VDD
0.7VDD+0.1
0.7VD+0.1
2.4
0.75VDD
0.9VDD
2.4
0.75VDD
0.9VDD
0.2VDD–0.1
0.2VDD–0.15
0.2VDD–0.25
0.2VDD–0.3
0.2VDD–0.35
0.2VDD–0.45
VDD+0.5
VDD+0.5
VDD+0.5
VDD+0.5
VDD+0.5
VDD+0.5
0.45
0.45
–50
–75
–75
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
ITL
Logical 1-to-0 transition current, ports 1, 2, 3
0 to +70°C
VIN = 2.0V
–40 to +85°C
–40 to +125°C
–650
–750
–750
µA
µA
µA
IL1 Input leakage current, port 0, EA
0.45V<Vi<VDD
±10 µA
IDD Power supply current:
Active mode @ 16MHz 1
Active mode @ 24MHz 1
Idle mode @ 16MHz 2
Idle mode @ 24MHz 2
Power down mode 3
See note 7
19 mA
29 mA
3.7 mA
5.6 mA
50 µA
RRST
Internal reset pull-down resistor
50 150 k
CIO Pin capacitance
f = 1MHz
10 pF
NOTES:
1. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5ns; VIL = VSS +0.5V;
VIH = VDD – 0.5V; XTAL2 not connected; EA = RST = Port 0 = VDD.
2. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 5ns; VIL = VSS +0.5V;
VIH = VDD – 0.5V; XTAL2 not connected; EA = Port 0 = VDD; RST = VSS.
3. The power-down current is measured with all output pins disconnected; XTAL2 not connected; EA = Port 0 = VDD; RST = XTAL1 = VSS.
4. Capacitive loading on Port 0 and Port 2 may cause spurious noise pulses to be superimposed on the LOW level output voltage of ALE, Port
1 and Port 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make a 1-to-0
transition during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE line may exceed 0.8V. In such
cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
5. Capacitive loading on Port 0 and Port 2 may cause the HIGH level output voltage on ALE and PSEN to momentarily fall below the 0.9VDD
specification when the address bits are stabilizing.
6. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per Port pin:
10mA
Maximum IOL per 8-bit port –
Port 0: 26mA
Ports 1, 2, and 3: 15mA
Maximum total IOL for all output pins: 71mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
7. See Figures 11 through 14 for IDD test conditions.
1998 Jul 03
11

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