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PDF TEA5040S Data sheet ( Hoja de datos )

Número de pieza TEA5040S
Descripción WIDE BAND VIDEO PROCESSOR
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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No Preview Available ! TEA5040S Hoja de datos, Descripción, Manual

TEA5040S
WIDE BAND VIDEO PROCESSOR
. DIGITAL CONTROL OF BRIGHTNESS,
SATURATION AND CONTRAST ON TV SIG-
NALS AND R, G, B INTERNAL OR EXTER-
NAL SOURCES
. BUS DRIVE OF SWITCHING FUNCTIONS
. DEMATRIXING OF R, G, B SIGNALS FROM
Y, R-Y, B-Y, TV MODE INPUTS
. MATRIXING OF R, G, B SOURCES INTO
Y, R-Y, B-Y SIGNALS
. AUTOMATIC DRIVE AND CUT-OFF CON-
TROLS BY DIGITAL PROCESSING DURING
FRAME RETRACE
. PEAK AND AVERAGE BEAM CURRENT LIMI-
TATION
. ON-CHIP SWITCHING FOR R, G, B INPUT
SELECTION
. ON-CHIP INSERTION OF INTERNAL OR EX-
TERNAL R, G, B SOURCES
DESCRIPTION
The TEA5040S is a serial bus-controlled video-
processing device which integrates a complex ar-
chitecture fulfilling multiple functions.
SDIP42
(Plastic Package)
ORDER CODE : TEA5040S
PIN CONNECTIONS
VCC
R INTERNAL INPUT
R EXTERNAL INPUT
G INTERNAL INPUT
G EXTERNAL INPUT
B INTERNAL INPUT
B EXTERNAL INPUT
FB EXTERNAL INPUT
FB INTERNAL INPUT
B-Y INPUT
R-Y INPUT
Y INPUT
CLOCK
DATA
ENABLE
VOLTAGE REFERENCE
R CLAMP MEMORY
G CLAMP MEMORY
B CLAMP MEMORY
GROUND
NOT TO BE CONNECTED
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42 SWITCHABLE VIDEO OUTPUT
41 SYNCHRO INPUT
40 INTERNAL VIDEO OUTPUT
39 INTERNAL VIDEO INPUT
38 AVERAGE BEAM LIMIT. REF
37 EXTERNAL VIDEO INPUT
36 AVERAGEBEAMCURRENTFILTER
35 LEAKAGE CURRENT FILTER
34 CATHODE CURRENT INPUT
33 SWITCH CUT-OFF RESISTANCE
32 SUPER SANDCASTLE INPUT
31 B OUTPUT
30 CUT-OFFMEMORY (B CHANNEL)
29 DRIVE MEMORY (B CHANNEL)
28 G OUTPUT
27 CUT-OFF MEMORY (G CHANNEL)
26 DRIVE MEMORY (G CHANNEL)
25 R OUTPUT
24 CUT-OFF MEMORY (R CHANNEL)
23 DRIVE MEMORY (R CHANNEL)
22 NOT TO BE CONNECTED
April 1993
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TEA5040S pdf
TEA5040S
which is stored by an external leakage capacitor
to be used later as a reference for the cut-off
current measurement.
- When a current due to a cut-off pulse occurs, the
voltage appearing on the pin 34 is compared
within the IC to the voltage present on the leakage
memory. An appropriate externalcapacitor is then
charged or discharged in such a way that the
difference between each measured current and
the leakage current is kept constant, and thus the
quasi cut-off current is kept constant.
Average Beam Current Limitation
The total current of the three guns is integrated by
means of an internal resistor and an external ca-
pacitor (pin 36) and then compared with a program-
mable voltage reference (pin 38). When 70% of the
maximum permitted beam current is reached, the
drive gain begins to be reduced ; to do so, the
amplitude of the inserted pulse is increased.
In order to keep enough contrast, the maximum
drive reduction is limited to 6dB. If it is not sufficient,
the brightness is suppressed.
SPECIFICATION FOR THE THOMSON BI-DI-
RECTIONAL DATA BUS
This is a bi-directional 3-wire (ENABLE, CLOCK,
DATA) serial bus. The DATA line transmission is
bi-directional whereas ENABLE and CLOCK lines
are only microprocessor controlled. The ENABLE
and CLOCK lines are only driven by the microcom-
puter.
Figure 1
µP
IC
I
IC
II
IC
III
It is possible to select several IC from the micro-
processor via the bus. The identification of each
particular IC is achieved by the length of the word
(number of data bits/clock pulses), meaning that
each IC responds with its own particular word
length.
The number is determined while ENABLE is low
and by counting the negative clock edges. As soon
as the high edge of the ENABLE signal is applied,
the number is fixed (see Figure 2).
The reply word lenght from any of the IC on the
bi-directional line is four bits. If it is found insufficient
then the reply word can be expandedto include two
repetitive reply sequences one after the other.
The bi-directional transmission is enabled if :
- the IC has been previously addressed at the
positive going edge of the enable pulse.
- ENABLE remains high,
and DATAis available only during the periodwhen
the clock remains low.
- number of identification bits : n
1...n : data from the microcomputer
- number of bi-directional clocks : 4
1...M : data to the microcomputer
The four bit reply word (synchronized with the clock
coming from the microcontroller) from the ad-
dressed IC to the microcontroller is sent only once.
Subsequent clock pulses present on the clock line
will be ignored by the IC in question. The data sent
to the microcontroller can generally be suppressed
completely or partially, but in the case of the video-
processor, a minimum reply word lenght of 1 has
to be maintained (see Figure 3).
This implies that a bi-directional bus that incorpo-
rates other IC’s together with a videoprocessor IC
is then also limited by the minimum reply word
restriction of 1.
The data word from the microcompter is divided
into :
- addresses within the IC
- data
The data word to the microcomputer is divided into
- two data bits,
- two address bits
After the operating voltage is applied, the first
transmission will be used as a reset command, i.e.
the data word will not be detected.
- number of identification bits : n
1...n : data from the microcomputer
- number of bi-directional clocks : 1
1 : data the microcomputer (which is the minimum
number for the videoprocessor)
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