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PDF TEA1522 Data sheet ( Hoja de datos )

Número de pieza TEA1522
Descripción STARplug
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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No Preview Available ! TEA1522 Hoja de datos, Descripción, Manual

INTEGRATED CIRCUITS
DATA SHEET
TEA152x family
STARplugTM
Product specification
File under Integrated Circuits, IC11
2000 Sep 08

1 page




TEA1522 pdf
Philips Semiconductors
STARplugTM
Product specification
TEA152x family
PINNING
SYMBOL
VCC
GND
RC
REG
SGND
AUX
SOURCE
n.c.
DRAIN
TEA152xP
1
2
3
4
5
6
7
8
PIN
TEA152xT
1
2, 3, 4, 5,
9 and 10
6
7
8
11
12 and 13
14
TEA152xAJM
1 supply voltage
2 ground
DESCRIPTION
3 frequency setting
4 regulation input
5
signal ground; connected to exposed die pad; must be
connected to pin 2
6
input for voltage from auxiliary winding for timing
(demagnetization)
7 source of internal MOS switch
8 not connected
9
drain of internal MOS switch; input for start-up current
and valley sensing
handbook, halfpage
VCC 1
8 DRAIN
GND 2
7 n.c.
TEA152xP
RC 3
6 SOURCE
REG 4
5 AUX
MGT420
Fig.2 Pin configuration of TEA152xP.
handbook, halfpage
VCC 1
GND 2
14 DRAIN
13 n.c.
GND 3
12 n.c.
GND 4 TEA152xT 11 SOURCE
GND 5
10 GND
RC 6
9 GND
REG 7
8 AUX
MGT421
Fig.3 Pin configuration of TEA152xT.
2000 Sep 08
handbook, halfpage
VCC 1
GND 2
RC 3
REG 4
SGND 5 TEA152xAJM
AUX 6
SOURCE 7
n.c. 8
DRAIN 9
MGT422
Fig.4 Pin configuration of TEA152xAJM.
5

5 Page





TEA1522 arduino
Philips Semiconductors
STARplugTM
Product specification
TEA152x family
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Duty factor regulator (pin REG)
VREG
GV(erroramp)
VREG(clamp)
input voltage
voltage gain of error amplifier
clamping voltage at pin REG
IREG = 6 mA
Valley switching (not implemented in TEA152xAJM versions)
dV/dtvalley
fvalley
dV/dt for valley recognition
ringing frequency for valley
switching
N × Vo = 100 V
td(valley-swon) delay from valley recognition to
switch-on
2.4 2.5 2.6 V
20 dB
− − 7.5 V
102
102 V/µs
200 550 800 kHz
150 ns
Current and short circuit winding protection
Vsource(max) maximum source voltage
td(propagation) delay from detecting VSRC(max) to
switch-off
dV/dt = 0.1 V/µs
dV/dt = 0.5 V/µs
Vswp
short circuit winding protection
voltage
dV/dt = 0.5 V/µs
tleb blanking time for current and short
circuit winding protection
0.47 0.50 0.53 V
160 185 ns
0.7 0.75 0.8 V
250 350 450 ns
Output stage (FET)
IL(drain)
V(BR)drain
RDS(on)
drain leakage current
drain breakdown voltage
drain-source on-state resistance
of TEA1520
drain-source on-state resistance
of TEA1521
drain-source on-state resistance
of TEA1522
drain-source on-state resistance
of TEA1523
drain-source on-state resistance
of TEA1524
tdrain(f)
drain fall time
Vdrain = 650 V
Tj > 0 °C
Tj = 25 °C; Isource = 0.06 A
Tj = 100 °C; Isource = 0.06 A
Tj = 25 °C; Isource = 0.125 A
Tj = 100 °C; Isource = 0.125 A
Tj = 25 °C; Isource = 0.25 A
Tj = 100 °C; Isource = 0.25 A
Tj = 25 °C; Isource = 0.5 A
Tj = 100 °C; Isource = 0.5 A
Tj = 25 °C; Isource = 1.0 A
Tj = 100 °C; Isource = 1.0 A
Vi = 300 V; no external capacitor at
drain
650
48
68
24
34
12
17
6.5
9.0
3.4
4.8
75
125 µA
V
55.2
78.2
27.6
39.1
13.8
19.6
7.5
10.0
3.9
5.5
ns
Temperature protection
Tprot(max)
Tprot(hys)
maximum temperature threshold
hysteresis temperature
150 160 170 °C
2 − °C
2000 Sep 08
11

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