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PDF TEA1205 Data sheet ( Hoja de datos )

Número de pieza TEA1205
Descripción High efficiency DC/DC converter
Fabricantes NXP Semiconductors 
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INTEGRATED CIRCUITS
DATA SHEET
TEA1205AT
High efficiency DC/DC converter
Preliminary specification
File under Integrated Circuits, IC03
1998 Mar 24

1 page




TEA1205 pdf
Philips Semiconductors
High efficiency DC/DC converter
Preliminary specification
TEA1205AT
PINNING
SYMBOL
VSEL
SYNC
OUT
SENSE
LX
GND
ILIM
SHDWN
PIN DESCRIPTION
1 output voltage selection input
2 synchronisation clock input
3 output voltage output
4 output voltage sense input
5 inductor connection
6 ground
7 current limit resistor connection
8 shut-down input
handbook, halfpage
VSEL 1
8 SHDWN
SYNC 2
7 ILIM
TEA1205AT
OUT 3
6 GND
SENSE 4
5 LX
MGM697
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
Control mechanism
The TEA1205AT DC/DC converter is able to operate in
discontinuous or continuous conduction operation.
All switching actions are completely determined by a
digital control circuit which uses the output voltage level as
its control input. This novel digital approach enables the
use of a new pulse width and frequency modulation
scheme, which ensures optimum power efficiency over the
complete range of operation of the converter. The scheme
works as follows. At low output power, a very small current
pulse is generated in the inductor, and the pulse rate
varies with a varying load. When the output voltage drops
below a specific limit, which indicates that the converter’s
current capability is not sufficient, the digital controller
switches to the next state of operation. The peak current in
the inductor is made higher, and the pulse rate can again
vary with a varying load. A third operation state is available
for again higher currents.
When high output power is requested, the device starts
operating in continuous conduction mode. This results in
minimum AC currents in the circuit components and hence
optimum efficiency, cost, and EMC. In this mode, the
output voltage is allowed to vary between two predefined
voltage levels. As long as the output voltage stays within
this so-called window, switching continues in a fixed
pattern. When the output voltage reaches one of the
window borders, the digital controller immediately reacts
by adjusting the pulse width and inserting a current step in
such a way that the output voltage stays within the window
with higher or lower current capability. This approach
enables very fast reaction to load variations. Figure 3
shows the various coil current waveforms for low and high
current capability in each power conversion mode.
Figure 4 shows the converter’s response to a sudden load
increase. The upper trace shows the output voltage.
The ripple on top of the DC level is a result of the current
in the output capacitor, which changes in sign twice per
cycle, times the capacitor’s internal Equivalent Series
Resistance (ESR). After each ramp-down of the inductor
current, i.e. when the ESR effect increases the output
voltage, the converter determines what to do in the next
cycle. As soon as more load current is taken from the
output the output voltage starts to decay. When the output
voltage becomes lower than the low limit of the window,
a corrective action is taken by a ramp-up of the inductor
current during a much longer time. As a result, the DC
current level is increased and normal continuous
conduction mode can continue. The output voltage
(including ESR effect) is again within the predefined
window.
Figure 5 depicts the spread of the output voltage window.
The absolute value is most dependent on spread, while the
actual window size is not affected. For one specific device,
the output voltage will not vary more than 4%.
Start-up
A possible deadlock situation in boost configuration can
occur after a sequence of disconnecting and reconnecting
the input voltage source. If, after disconnection of the input
source, the output voltage falls below 2.0 V, the device
may not restart properly after reconnection of the input
source, and may take continuous current from the input.
An external circuit to prevent the deadlock situation is
shown in Chapter “Application information”.
Shut-down
When the shut-down pin is made HIGH, the converter
disables both switches and power consumption is reduced
to a few µA.
1998 Mar 24
5

5 Page





TEA1205 arduino
Philips Semiconductors
High efficiency DC/DC converter
APPLICATION INFORMATION
Preliminary specification
TEA1205AT
handbook, full pagewidth
L1
VI
C1
D1
OUT
LX
TEA1205AT
SENSE
GND ILIM VSEL SYNC SHDWN
Rlim
VO
C2
MGM701
Fig.8 Complete application for upconversion.
A typical component choice for an upconverter from
3 NiCd cells or one Li-ion cell to 5.0 V in a GSM handset
(peak power 7.5 W, peak current 2.7 A) is (see Fig.8):
L1 = 10 µH; Isat > 2.3 A; low DC resistance, e.g.
Coilcraft DO3308-103
C1 = 100 µF; low ESR capacitor; necessity depends on
type of input voltage source
C2 = 330 µF; ESR = 0.1 ; e.g. Sprague 595D series
D1; medium power Schottky diode; e.g. Philips
PRLL5819.
For lower power applications, the Isat and RDC values of
the inductor can be scaled back by the scaling factor of the
output current from the values above. The same holds for
the ESR value of the output capacitor. A further
improvement is increase of inductance and decrease of
output capacitance.
An additional circuit to prevent start-up deadlock in
upconversion is shown in Fig.9. The function of TR1, R1
and R2 is to put the converter into shut-down mode when
the input source is suddenly disconnected. The circuit
operates as follows. When VI is present, TR1 conducts
and the SHDWN pin is kept LOW. As soon as VI falls below
1 V, TR1 no longer conducts and the device is put into
shut-down before VO falls below 2 V. In the event that a
signal is available which indicates the presence of the
input voltage source, this signal should be applied to the
SHDWN pin. TR1, R1 and R2 should be omitted in that
case.
More application information can be found in the
associated application note.
handbook, halfpage
VI
R2
2.7 M
VO
R1
1 M
SHDWN
TR1
MGK930
Fig.9 External deadlock prevention circuit.
1998 Mar 24
11

11 Page







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