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PDF TEA1202TS Data sheet ( Hoja de datos )

Número de pieza TEA1202TS
Descripción Battery power unit
Fabricantes NXP Semiconductors 
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No Preview Available ! TEA1202TS Hoja de datos, Descripción, Manual

INTEGRATED CIRCUITS
DATA SHEET
TEA1202TS
Battery power unit
Objective specification
File under Integrated Circuits, IC03
2000 Jun 08

1 page




TEA1202TS pdf
Philips Semiconductors
Battery power unit
Objective specification
TEA1202TS
PINNING
SYMBOL
LX1
SHDWN0
SHDWN2
UPOUT/DNIN
ILIM
OUT1
FB1
GND
FB2
OUT2
IN2
LBI2
LBI1
LBO
Vref
FB0
GND0
SYNC/PWM
U/D
LX2
PIN DESCRIPTION
1 inductor connection 1
2 DC/DC shut-down input
3 LDO2 shut-down input
4 up mode: DC/DC output;
down mode DC/DC input
5 current limiting resistor
connection
6 LDO1 output
7 LDO1 feedback input
8 internal supply ground
9 LDO2 feedback input
10 LDO2 output
11 LDO2 input
12 low battery detector input 2
13 low battery detector input 1
14 low battery detector output
15 reference voltage
16 DC/DC feedback input
17 DC/DC converter ground
18 synchronization clock input or
PWM-only selection input
19 conversion mode selection input
20 inductor connection 2
handbook, halfpage
LX1 1
20 LX2
SHDWN0 2
19 U/D
SHDWN2 3
18 SYNC/PWM
UPOUT/DNIN 4
17 GND0
ILIM 5
16 FB0
TEA1202TS
OUT1 6
15 Vref
FB1 7
14 LBO
GND 8
13 LBI1
FB2 9
12 LBI2
OUT2 10
11 IN2
MGU060
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
Control mechanism
The TEA1202TS DC/DC converter is able to operate in
PFM (discontinuous conduction) or PWM (continuous
conduction) operating mode. All switching actions are
completely determined by a digital control circuit which
uses the output voltage level as its control input. This novel
digital approach enables the use of a new pulse width and
frequency modulation scheme, which ensures optimum
power efficiency over the complete range of operation of
the converter.
When high output power is requested, the device will
operate in PWM (continuous conduction) operating mode.
This results in minimum AC currents in the circuit
components and hence optimum efficiency, minimum
costs and low EMC. In this operating mode, the output
voltage is allowed to vary between two predefined voltage
levels. As long as the output voltage stays within this
so-called window, switching continues in a fixed pattern.
When the output voltage reaches one of the window
borders, the digital controller immediately reacts by
adjusting the pulse width and inserting a current step in
such a way that the output voltage stays within the window
with higher or lower current capability. This approach
enables very fast reaction to load variations. Figure 3
shows the response of the converter to a sudden load
increase. The upper trace shows the output voltage.
The ripple on top of the DC level is a result of the current
in the output capacitor, which changes in sign twice per
cycle, times the internal Equivalent Series Resistance
(ESR) of the capacitor. After each ramp-down of the
inductor current, i.e. when the ESR effect increases the
output voltage, the converter determines what to do in the
next cycle. As soon as more load current is taken from the
output the output voltage starts to decay.
2000 Jun 08
5

5 Page





TEA1202TS arduino
Philips Semiconductors
Battery power unit
Objective specification
TEA1202TS
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP.
DIGITAL INPUT LEVELS
VlL(n)
LOW-level input voltage on all
digital pins
0
VIH(n)
HIGH-level input voltage
on pins SYNC/PWM,
SHDWN0 and SHDWN2
note 7
0.55V4
all other digital input pins
V4 0.4
Low dropout voltage regulators; note 8
VLDO
Vdropout
Vdrop
output voltage range
dropout voltage
minimum drop voltage for
functionality within
specification
VLDO < V4 + 0.4 V
ILDO = 50 mA; note 9
ILDO = 50 mA
1.30
−−
250
ILDO(max)
VLDO
Vline
Vload
PSRR
maximum output current
output voltage accuracy
line voltage regulation
load voltage regulation
power supply ripple rejection
in regulation
VI VLDO = 2 V; ILDO = 10 µA
VI VLDO > Vdrop
10 µA < ILDO < 50 mA
note 10
2.0
25
50
tres response time
Iq(LDO)
Ishdwn(LDO)
quiescent current
shut-down current
after load step from no load to
ILDO(max)
200
50
SWITCH CIRCUIT
RDSon
drain-to-source resistance in VFB1,2 > 2 V; Tj = 27 °C
200
switched-on state
IO(max)
maximum output current in
switched-on state
VFB1,2 > 2 V
0.40 0.45
Low battery detector
ILBD
tt(HL)
supply current of detector
transition time
DETECTION INPUT PIN LBI1
Vdet low battery detection level
Vhys low battery detection
hysteresis
TCVdet
temperature coefficient of
detection level
TCVhys
temperature coefficient of
detection hysteresis
VI = 0.9 V
falling Vbat
falling Vbat
20
2
0.88 0.90
36 40
0
0.175
DETECTION OUTPUT PIN LB0
IO(sink)
output sink current
15
MAX. UNIT
0.4 V
V4 + 0.3 V
V4 + 0.3 V
5.50 V
75 mV
mV
mA
+2.0 %
1 mV
1 mV
dB
− µs
− µA
1 µA
m
0.50 A
− µA
− µs
0.92 V
44 mV
mV/K
mV/K
− µA
2000 Jun 08
11

11 Page







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