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PDF TEA1200TS Data sheet ( Hoja de datos )

Número de pieza TEA1200TS
Descripción 0.95 V starting DC-to-DC converter with low battery indicator
Fabricantes NXP Semiconductors 
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No Preview Available ! TEA1200TS Hoja de datos, Descripción, Manual

INTEGRATED CIRCUITS
DATA SHEET
TEA1200TS
0.95 V starting DC-to-DC converter
with low battery indicator
Product specification
2002 May 14

1 page




TEA1200TS pdf
Philips Semiconductors
0.95 V starting DC-to-DC converter
with low battery indicator
Product specification
TEA1200TS
PINNING
SYMBOL
LX1
SHDWN0
UPOUT/DNIN
UPOUT/DNIN
ILIM
n.c.
Vref
GND
LBI1
LBO
Vref
FB0
GND0
SYNC/PWM
U/D
LX2
PIN DESCRIPTION
1 inductor connection 1
2 DC-to-DC converter shut-down
input
3 up mode: DC-to-DC converter
output; down mode DC-to-DC
converter input
4 up mode: DC-to-DC converter
output; down mode DC-to-DC
converter input
5 current limiting resistor
connection
6 not connected
7 reference voltage input
8 internal supply ground
9 low battery detector input 1
10 low battery detector output
11 reference voltage input
12 DC-to-DC converter feedback
input
13 DC-to-DC converter ground
14 synchronization clock input or
PWM-only selection input
15 conversion mode selection input
16 inductor connection 2
handbook, halfpage
LX1 1
16 LX2
SHDWN0 2
15 U/D
UPOUT/DNIN 3
14 SYNC/PWM
UPOUT/DNIN 4
13 GND0
TEA1200TS
ILIM 5
12 FB0
n.c. 6
Vref 7
GND 8
11 Vref
10 LBO
9 LBI1
MBL419
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
Control mechanism
The TEA1200TS DC-to-DC converter is able to operate in
the PFM (discontinuous conduction) or PWM (continuous
conduction) operating mode. All switching actions are
completely determined by a digital control circuit which
uses the output voltage level as its control input. This novel
digital approach enables the use of a new pulse width and
frequency modulation scheme, which ensures optimum
power efficiency over the complete range of operation of
the converter.
When high output power is requested, the device will
operate in the PWM operating mode. This results in
minimum AC currents in the circuit components and hence
optimum efficiency, minimum costs and low EMC. In this
operating mode, the output voltage is allowed to vary
between two predefined voltage levels. As long as the
output voltage stays within this so-called window,
switching continues in a fixed pattern.
When the output voltage reaches one of the window
borders, the digital controller immediately reacts by
adjusting the pulse width and inserting a current step in
such a way that the output voltage stays within the window
with higher or lower current capability. This approach
enables very fast reaction to load variations. Figure 3
shows the response of the converter to a sudden load
increase. The upper trace shows the output voltage.
The ripple on top of the DC level is a result of the current
in the output capacitor, which changes in sign twice per
cycle, times the internal Equivalent Series Resistance
(ESR) of the capacitor. After each ramp-down of the
inductor current, i.e. when the ESR effect increases the
output voltage, the converter determines what to do in the
next cycle. As soon as more load current is taken from the
output the output voltage starts to decay.
2002 May 14
5

5 Page





TEA1200TS arduino
Philips Semiconductors
0.95 V starting DC-to-DC converter
with low battery indicator
Product specification
TEA1200TS
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
DIGITAL INPUT LEVELS
VlL(n)
LOW-level input voltage on all
digital pins
VIH(n)
HIGH-level input voltage
on pins SYNC/PWM,
SHDWN0 and SHDWN2
all other digital input pins
note 7
Low battery detector
tt(HL)
HIGH-to-LOW transition time
DETECTION INPUT PIN LBI1
falling VBAT
Vdet(LB)
Vhys(LB)
low battery detection level
low battery detection
hysteresis
falling VBAT
TCVdet
temperature coefficient of
detection level
TCVhys
temperature coefficient of
detection hysteresis
0 0.4 V
0.55V4
V4 0.4
V4 + 0.3 V
V4 + 0.3 V
2 − µs
0.87 0.90 0.93 V
20 mV
0 mV/K
0.175 mV/K
DETECTION OUTPUT PIN LB0
Io(sink)
output sink current
General characteristics
15 − − µA
Vref reference voltage
Iq
quiescent current at pin
all blocks operating
UPOUT/DNIN
1.165
1.190
270
1.215
V
µA
Tamb
Tmax
ambient temperature
internal temperature for cut-off
20 +25 +80 °C
190 − °C
Notes
1. The undervoltage lockout level shows wide specification limits since it decreases with increasing temperature. When
the temperature increases, the minimum supply voltage of the digital control part of the IC decreases and therefore
the correct operation of this function is guaranteed over the whole temperature range. The undervoltage lockout level
is measured at pin UPOUT/DNIN.
2. When Vi is lower than the target output voltage but higher than 2.2 V, the P-type power MOSFET will remain
conducting (duty factor is 100%), resulting in Vo following Vi.
3. The quiescent current is specified as the input current in the upconversion configuration at Vi = 1.20 V and
Vo = 3.30 V, using L1 = 6.8 µH, R1 = 150 kand R2 = 91 k.
4. The current limit is defined by resistor R10. This resistor must be 1% accurate.
5. The specified efficiency is valid when using an output capacitor having an ESR of 0.1 and an inductor of 6.8 µH
with an ESR of 0.05 and a sufficient saturation current level.
6. The specified start-up time is the time between the connection of a 1.20 V input voltage source and the moment the
output reaches 3.30 V. The output capacitance equals 100 µF, the inductance equals 6.8 µH and no load is present.
7. V4 is the voltage at pin UPOUT/DNIN. If the applied HIGH-level voltage is less than V4 1 V, the quiescent current
of the device will increase.
2002 May 14
11

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