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PDF TE28F320C3B110 Data sheet ( Hoja de datos )

Número de pieza TE28F320C3B110
Descripción 3 VOLT ADVANCED+ BOOT BLOCK 8-/ 16-/ 32-MBIT FLASH MEMORY FAMILY
Fabricantes Intel Corporation 
Logotipo Intel Corporation Logotipo



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PRODUCT PREVIEW
3 VOLT ADVANCED+ BOOT BLOCK
8-, 16-, 32-MBIT
FLASH MEMORY FAMILY
28F008C3, 28F016C3, 28F032C3
28F800C3, 28F160C3, 28F320C3
n Flexible SmartVoltage Technology
2.7 V–3.6 V Read/Program/Erase
2.7 V or 1.65 V I/O Option Reduces
Overall System Power
12 V for Fast Production
Programming
n High Performance
2.7 V–3.6 V: 90 ns Max Access Time
3.0 V–3.6 V: 80 ns Max Access Time
n Optimized Architecture for Code Plus
Data Storage
Eight 8-Kbyte Blocks,
Top or Bottom Locations
Up to Sixty-Three 64-KB Blocks
Fast Program Suspend Capability
Fast Erase Suspend Capability
n Flexible Block Locking
Lock/Unlock Any Block
Full Protection on Power-Up
WP# Pin for Hardware Block
Protection
VPP = GND Option
VCC Lockout Voltage
n Low Power Consumption
9 mA Typical Read Power
10 µA Typical Standby Power with
Automatic Power Savings Feature
n Extended Temperature Operation
–40 °C to +85 °C
n Easy-12 V
Faster Production Programming
No Additional System Logic
n 128-bit Protection Register
64-bit Unique Device Identifier
64-bit User Programmable OTP
Cells
n Extended Cycling Capability
Minimum 100,000 Block Erase
Cycles
n Flash Data Integrator Software
Flash Memory Manager
System Interrupt Manager
Supports Parameter Storage,
Streaming Data (e.g., voice)
n Automated Word/Byte Program and
Block Erase
Command User Interface
Status Registers
n SRAM-Compatible Write Interface
n Cross-Compatible Command Support
Intel Basic Command Set
Common Flash Interface
n x 16 for High Performance
48-Ball µBGA* Package
48-Lead TSOP Package
n x 8 I/O for Space Savings
48-Ball µBGA* Package
40-Lead TSOP Package
n 0.25 µ ETOX™ VI Flash Technology
The 0.25 µm 3 Volt Advanced+ Boot Block, manufactured on Intel’s latest 0.25 µ technology, represents a
feature-rich solution at overall lower system cost. Smart 3 flash memory devices incorporate low voltage
capability (2.7 V read, program and erase) with high-speed, low-power operation. Flexible block locking
allows any block to be independently locked or unlocked. Add to this the Intel-developed Flash Data
Integrator (FDI) software and you have a cost-effective, flexible, monolithic code plus data storage solution on
the market today. 3 Volt Advanced+ Boot Block products will be available in 48-lead TSOP, 40-lead TSOP,
and 48-ball µBGA* packages. Additional information on this product family can be obtained by accessing
Intel’s WWW page: http://www.intel.com/design/flcomp.
May 1998
Order Number: 290645-001

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TE28F320C3B110 pdf
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3 VOLT ADVANCED+ BOOT BLOCK
1.0 INTRODUCTION
This document contains the specifications for the
3 Volt Advanced+ Boot Block flash memory family.
These flash memories add features which can be
used to enhance the security of systems: instant
block locking and a protection register.
Throughout this document, the term “2.7 V” refers
to the full voltage range 2.7 V–3.6 V (except where
noted otherwise) and “VPP = 12 V” refers to 12 V
±5%. Sections 1 and 2 provide an overview of the
flash memory family including applications, pinouts,
pin descriptions and memory organization. Section
3 describes the operation of these products. Finally,
Section 4 contains the operating specifications.
1.1 3 Volt Advanced+ Boot Block
Flash Memory Enhancements
The 3 Volt Advanced+ Boot Block flash memory
features:
Zero-latency, flexible block locking
128-bit Protection Register
Simple system implementation for 12 V
production programming with 2.7 V in-field
programming
Ultra-low power operation at 2.7 V
Minimum 100,000 block erase cycles
Common Flash Interface for software query of
device specs and features
Table 1. 3 Volt Advanced+ Boot Block Feature Summary
Feature
8 M(2)
16 M
32 M(1)
8 M(2)
16 M
32 M
Reference
VCC Operating Voltage
2.7 V – 3.6 V
Table 8
VPP Voltage
Provides complete write protection with
optional 12V Fast Programming
Table 8
VCCQ I/O Voltage
2.7 V– 3.6 V
Note 3
Bus Width
8-bit
16-bit
Table 2
Speed (ns)
90, 110 @ 2.7 V and 80, 100 @ 3.0 V
Table 11
Blocking (top or bottom)
8 x 8-Kbyte parameter
4-Mb: 7 x 64-Kbyte main
8-Mb: 15 x 64-Kbyte main
16-Mb: 31 x 64-Kbyte main
32-Mb: 63 x 64-Kbyte main
8 x 4-Kword parameter
4-Mb: 7 x 32-Kword main 8-
Mb: 15 x 32-Kword main
16-Mb: 31 x 32-Kword main
32-Mb: 63 x 32-Kword main
Section 2.2
Appendix E and F
Operating Temperature
Extended: –40 °C to +85 °C
Table 8
Program/Erase Cycling
100,000 cycles
Table 8
Packages
40-Lead TSOP(1)
48-Ball µBGA* CSP(2)
48-Lead TSOP
48-Ball µBGA* CSP(2)
Figures 1, 2, 3,
and 4
Block Locking
Flexible locking of any block with zero latency
Section 3.3
Protection Register
64-bit unique device number, 64-bit user programmable Section 3.4
NOTES:
1. 32-Mbit density not available in 40-lead TSOP.
2. 8-Mbit density not available in µBGA* CSP.
3. VCCQ operation at 1.65 V — 2.5 V available upon request.
PRODUCT PREVIEW
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TE28F320C3B110 arduino
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3 VOLT ADVANCED+ BOOT BLOCK
3.0 PRINCIPLES OF OPERATION
The 3 Volt Advanced+ Boot Block flash memory
family utilizes a CUI and automated algorithms to
simplify program and erase operations. The CUI
allows for 100% CMOS-level control inputs and
fixed power supplies during erasure and
programming.
The internal WSM completely automates program
and erase operations while the CUI signals the start
of an operation and the status register reports
status. The CUI handles the WE# interface to the
data and address latches, as well as system status
requests during WSM operation.
the VPP voltage. The appropriate read mode
command must be issued to the CUI to enter the
corresponding mode. Upon initial device power-up
or after exit from reset, the device automatically
defaults to read array mode.
CE# and OE# must be driven active to obtain data
at the outputs. CE# is the device selection control;
when active it enables the flash memory device.
OE# is the data output control and it drives the
selected memory data onto the I/O bus. For all read
modes, WE# and RP# must be at VIH. Figure 9
illustrates a read cycle.
3.1.2
OUTPUT DISABLE
3.1 Bus Operation
The 3 Volt Advanced+ Boot Block flash memory
devices read, program and erase in-system via the
local CPU or microcontroller. All bus cycles to or
from the flash memory conform to standard
microcontroller bus cycles. Four control pins dictate
the data flow in and out of the flash component:
CE#, OE#, WE# and RP#. These bus operations
are summarized in Table 3.
3.1.1
READ
The flash memory has four read modes available:
read array, read configuration, read status and read
query. These modes are accessible independent of
With OE# at a logic-high level (VIH), the device
outputs are disabled. Output pins are placed in a
high-impedance state.
3.1.3
STANDBY
Deselecting the device by bringing CE# to a logic-
high level (VIH) places the device in standby mode,
which substantially reduces device power
consumption without any latency for subsequent
read accesses. In standby, outputs are placed in a
high-impedance state independent of OE#. If
deselected during program or erase operation, the
device continues to consume active power until the
program or erase operation is complete.
Table 3. Bus Operations(1)
Mode
Read (Array, Status,
Configuration, or Query)
Note
2-4
RP#
VIH
CE#
VIL
OE#
VIL
WE#
VIH
DQ0–7
DOUT
DQ8-15
DOUT
Output Disable
2 VIH VIL VIH VIH High Z High Z
Standby
2 VIH VIH X
X High Z High Z
Reset
2,7 VIL
X
X
X High Z High Z
Write
2,5-7
VIH
VIL
VIH
VIL
DIN
DIN
NOTES:
1. 8-bit devices use only DQ[0:7], 16-bit devices use DQ[0:15]
2. X must be VIL, VIH for control pins and addresses.
3. See DC Characteristics for VPPLK, VPP1, VPP2, VPP3, voltages.
4. Manufacturer and device codes may also be accessed in read configuration mode (A1–A20 = 0). See Table 4.
5. Refer to Table 5 for valid DIN during a write operation.
6. To program or erase the lockable blocks, hold WP# at VIH.
7. RP# must be at GND ± 0.2 V to meet the maximum deep power-down current specified.
PRODUCT PREVIEW
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