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PDF TE28F004BVT80 Data sheet ( Hoja de datos )

Número de pieza TE28F004BVT80
Descripción 4-MBIT (256K X 16/ 512K X 8)SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
Fabricantes Intel Corporation 
Logotipo Intel Corporation Logotipo



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PRELIMINARY
4-MBIT (256K X 16, 512K X 8)
SmartVoltage BOOT BLOCK FLASH
MEMORY FAMILY
28F400BV-T/B, 28F400CV-T/B, 28F004BV-T/B
28F400CE-T/B, 28F004BE-T/B
n Intel SmartVoltage Technology
5V or 12V Program/Erase
2.7V, 3.3V or 5V Read Operation
Increased Programming Throughput
at 12V VPP
n Very High-Performance Read
5V: 60/80/120 ns Max. Access Time,
30/40 ns Max. Output Enable Time
3V: 110/150/180 ns Max Access
65/90 ns Max. Output Enable Time
2.7V: 120 ns Max Access 65 ns Max.
Output Enable Time
n Low Power Consumption
Max 60 mA Read Current at 5V
Max 30 mA Read Current at
2.7V–3.6V
n x8/x16-Selectable Input/Output Bus
28F400 for High Performance 16- or
32-bit CPUs
n x8-Only Input/Output Architecture
28F004B for Space-Constrained
8-bit Applications
n Optimized Array Blocking Architecture
One 16-KB Protected Boot Block
Two 8-KB Parameter Blocks
One 96-KB Main Block
Three 128-KB Main Blocks
Top or Bottom Boot Locations
n Absolute Hardware-Protection for Boot
Block
n Software EEPROM Emulation with
Parameter Blocks
n Extended Temperature Operation
–40°C to +85°C
n Extended Cycling Capability
100,000 Block Erase Cycles
(Commercial Temperature)
10,000 Block Erase Cycles
(Extended Temperature)
n Automated Word/Byte Program and
Block Erase
Industry-Standard Command User
Interface
Status Registers
Erase Suspend Capability
n SRAM-Compatible Write Interface
n Automatic Power Savings Feature
1 mA Typical ICC Active Current in
Static Operation
n Reset/Deep Power-Down Input
0.2 µA ICCTypical
Provides Reset for Boot Operations
n Hardware Data Protection Feature
Write Lockout during Power
Transitions
n Industry-Standard Surface Mount
Packaging
40-Lead TSOP
44-Lead PSOP: JEDEC ROM
Compatible
48-Lead TSOP
56-Lead TSOP
n Footprint Upgradeable from 2-Mbit and
to 8-Mbit Boot Block Flash Memories
n ETOX™ IV Flash Technology
July 1997
Order Number: 290530-005

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TE28F004BVT80 pdf
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4-MBIT SmartVoltage BOOT BLOCK FAMILY
1.0 PRODUCT FAMILY OVERVIEW
This datasheet contains the specifications for the
two branches of products in the SmartVoltage
4-Mbit boot block flash memory family: the -BE/CE
suffix products feature a low VCC operating range
of 2.7V–3.6V; the -BV/CV suffix products offer
3.0V–3.6V operation. Both BE/CE and BV/CV
products also operate at 5V for high-speed access
times. Throughout this datasheet, the 28F400
refers to all x8/x16 4-Mbit products, while
28F004B refers to all x8 4-Mbit boot block
products. Also, the term “2.7V” generally refers to
the full voltage range 2.7V–3.6V. Section 1
provides an overview of the flash memory family
including applications, pinouts and pin
descriptions. Sections 2 and 3 describe the
memory organization and operation for these
products. Finally, Sections 4 and 5 contain the
family’s operating specifications.
1.1 New Features in the
SmartVoltage Products
The SmartVoltage boot block flash memory family
offers identical operation with the BX/BL 12V
program products, except for the differences listed
below. All other functions are equivalent to current
products, including signatures, write commands,
and pinouts.
WP# pin has replaced a DU (Don’t Use) pin.
Connect the WP# pin to control signal or to
VCC or GND (in this case, a logic-level signal
can be placed on DU pin). See Tables 2 and
9 to see how the WP# pin works.
5V program/erase operation has been added.
If switching VPP for write protection, switch to
GND (not 5V) for complete write protection. To
take advantage of 5V write-capability, allow for
connecting 5V to VPP and disconnecting 12V
from VPP line.
Enhanced circuits optimize low VCC
performance, allowing operation down to
VCC = 2.7V (using the BE product).
If you are using BX/BL 12V VPP boot block
products today, you should account for the
differences listed above and also allow for
connecting 5V to VPP and disconnecting 12V from
VPP line, if 5V writes are desired.
1.2 Main Features
Intel’s SmartVoltage technology is the most
flexible voltage solution in the flash industry,
providing two discrete voltage supply pins: VCC for
read operation, and VPP for program and erase
operation. Discrete supply pins allow system
designers to use the optimal voltage levels for
their design. The 28F400BV/CV, 28F004BV,
28F400CE and 28F004BE provide program/erase
capability at 5V or 12V. The 28F400BV/CV and
28F004BV allow reads with VCC at 3.3 ± 0.3V or
5V, while the 28F400CE and 28F004BE allow
reads with VCC at 2.7V–3.6V or 5V. Since many
designs read from the flash memory a large
percentage of the time, read operation using the
2.7V or 3.3V ranges can provide great power
savings. If read performance is an issue, however,
5V VCC provides faster read access times.
Product
Name
28F004BV-T/B
28F400BV-T/B
28F400CV-T/B
28F004BE-T/B
28F400CE-T/B
Table 1. SmartVoltage Provides Total Voltage Flexibility
Bus
Width
2.7V–3.6V
VCC
3.3 ± 0.3V
5V ± 5%
5V ± 10%
VPP
5V ± 10% 12V ± 5%
x8 √ √ √ √
x8 or x16
√√√√
x8 or x16
√√√√
x8
√√√
x8 or x16
√√√
PRELIMINARY
5

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TE28F004BVT80 arduino
E
4-MBIT SmartVoltage BOOT BLOCK FAMILY
1.5 Pin Descriptions
Table 2. 28F400/004 Pin Descriptions
Symbol
A0–A18
A9
Type
INPUT
INPUT
Name and Function
ADDRESS INPUTS for memory addresses. Addresses are internally latched
during a write cycle. The 28F400 only has A0– A17 pins, while the 28F004B
has A0– A18.
ADDRESS INPUT: When A9 is at VHH the signature mode is accessed. During
this mode, A0 decodes between the manufacturer and device IDs. When BYTE#
is at a logic low, only the lower byte of the signatures are read. DQ15/A–1 is a
don’t care in the signature mode when BYTE# is low.
DQ0–DQ7
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle
during a Program command. Inputs commands to the Command User Interface
when CE# and WE# are active. Data is internally latched during the write cycle.
Outputs array, Intelligent Identifier and Status Register data. The data pins float to
tri-state when the chip is de-selected or the outputs are disabled.
DQ8–DQ15
CE#
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle
during a Program command. Data is internally latched during the write cycle.
Outputs array data. The data pins float to tri-state when the chip is de-selected or
the outputs are disabled as in the byte-wide mode (BYTE# = “0”). In the byte-wide
mode DQ15/A–1 becomes the lowest order address for data output on DQ0–DQ7.
The 28F004B does not include these DQ8–DQ15 pins.
INPUT
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and
sense amplifiers. CE# is active low. CE# high de-selects the memory device and
reduces power consumption to standby levels. If CE# and RP# are high, but not
at a CMOS high level, the standby current will increase due to current flow
through the CE# and RP# input stages.
OE#
INPUT OUTPUT ENABLE: Enables the device’s outputs through the data buffers during
a read cycle. OE# is active low.
WE#
INPUT
WRITE ENABLE: Controls writes to the Command Register and array blocks.
WE# is active low. Addresses and data are latched on the rising edge of the WE#
pulse.
RP#
INPUT RESET/DEEP POWER-DOWN: Uses three voltage levels (VIL, VIH, and VHH) to
control two different functions: reset/deep power-down mode and boot block
unlocking. It is backwards-compatible with the BX/BL/BV products.
When RP# is at logic low, the device is in reset/deep power-down mode,
which puts the outputs at High-Z, resets the Write State Machine, and draws
minimum current.
When RP# is at logic high, the device is in standard operation. When RP#
transitions from logic-low to logic-high, the device defaults to the read array mode.
When RP# is at VHH, the boot block is unlocked and can be programmed or
erased. This overrides any control from the WP# input.
PRELIMINARY
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