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PDF TDK5101 Data sheet ( Hoja de datos )
| Número de pieza | TDK5101 | |
| Descripción | ASK/FSK Transmitter 315 MHz | |
| Fabricantes | Infineon Technologies AG | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de TDK5101 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Wireless Components
ASK/FSK Transmitter 315 MHz
TDK 5101 Version 1.0
Specification October 2002
Preliminary
1 page  
TDK 5101
Product Description
2.1 Overview
The TDK 5101 is a single chip ASK/FSK transmitter for the frequency band 311-
317 MHz. The IC offers a high level of integration and needs only a few external
components. The device contains a fully integrated PLL synthesizer and a high
efficiency power amplifier to drive a loop antenna. A special circuit design and
an unique power amplifier design are used to save current consumption and
therefore to save battery life. Additional features like a power down mode, a low
power detect and a divided clock output are implemented. The IC can be used
for both ASK and FSK modulation.
2.2 Applications
s Keyless entry systems
s Remote control systems
s Alarm systems
s Communication systems
2.3 Features
s fully integrated frequency synthesizer
s VCO without external components
s high efficiency power amplifier
s frequency range 311 MHz ... 317 MHz
s ASK/FSK modulation
s low supply current (typically 7 mA)
s voltage supply range 2.1 V ... 4 V
s temperature range -40°C ... 125°C
s power down mode
s low voltage sensor
s programmable divided clock output for µC
s low external component count
Wireless Components
2-2
Specification, October 2002
5 Page 
TDK 5101
Functional Description
8 CLKOUT
VS
300 Ω
8
Clock output to supply an external device.
An external pull-up resistor has to be added
in accordance to the driving requirements of
the external device.
A clock frequency of 2.46 MHz is selected
by a logic low at CLKDIV input (pin9).
A clock frequency of 615 kHz is selected by
a logic high at CLKDIV input (pin9).
9 CLKDIV
This pin is used to select the desired clock
VS +1.2 V
VS
division rate for the CLKOUT signal.
A logic low (CLKDIV < 0.2 V) applied to this
pin selects the 2.46 MHz output signal at
5 µA CLKOUT (pin 8).
9 60 kΩ A logic high (CLKDIV open) applied to this
+0.8 V pin selects the 615 kHz output signal at
60 kΩ
CLKOUT (pin 8).
10 COSC
VS
6 kΩ
VS
10
100 µA
This pin is connected to the reference oscil-
lator circuit.
The reference oscillator is working as a neg-
ative impedance converter. It presents a
negative resistance in series to an induc-
tance at the COSC pin.
11 FSKOUT
12 FSKGND
VS VS
200 µA
1.5 kΩ
11
12
This pin is connected to a switch to
FSKGND (pin 12).
The switch is closed when the signal at
FSKDTA (pin 7) is in a logic low state.
The switch is open when the signal at
FSKDTA (pin 7) is in a logic high state.
FSKOUT can switch an additional capacitor
to the reference crystal network to pull the
crystal frequency by an amount resulting in
the desired FSK frequency shift of the trans-
mitter output frequency.
Ground connection for FSK modulation out-
put FSKOUT.
Wireless Components
3-5
Specification, October 2002
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TDK5101.PDF ] | |
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