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PDF TDAT04622 Data sheet ( Hoja de datos )
| Número de pieza | TDAT04622 | |
| Descripción | TDAT SONET/SDH 155/622/2488 Mbits/s Data Interfaces | |
| Fabricantes | Agere Systems | |
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Data Addendum
May 2001
TDAT SONET/SDH
155/622/2488 Mbits/s Data Interfaces
Introduction
The TDAT data interface is available in three different configurations as summarized in Table 1.
TDAT04622
The TDAT04622 device contains a subset of the TDAT042G5 device. The TDAT04622 device functions as
described in the TDAT042G5 SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet
(DS98-193SONT-4) with the following limitations:
s Quad OC-3 operation only or single OC-12 operation only.
s Single UTOPIA port.
TDAT021G2
The TDAT021G2 device contains a subset of the TDAT042G5 device. The TDAT021G2 device functions as
described in the TDAT042G5 SONET/SDH 155/622/2488 Mbits/s Data Interface Data Sheet
(DS98-193SONT-4) with the following limitations:
s Quad OC-3 operation only or dual OC-12 operation only.
s Two UTOPIA ports.
TDAT042G5
The TDAT042G5 device contains all functionality as described in the TDAT042G5 SONET/SDH 155/622/2488
Mbits/s Data Interface Data Sheet (DS98-193SONT-4).
Table 1. TDAT Device Product Line
Device
TDAT04622
OC-3
4
(A, B, C, D)
Line Ports
OC-12
1
(A)
TDAT021G2
4
(A, B, C, D)
2
(A, B)
OC-48
NA
NA
TDAT042G5
4
(A, B, C, D)
4
(A, B, C, D)
1
(16-bit parallel
multiplexed/
demultiplexed)
UTOPIA Ports
Ports Present
Modes
1
(A)
2
(A, B)
4
(A, B, C, D)
U2, U2+, U3, U3+
s 8-bit
s 16-bit
U2, U2+, U3, U3+
s 8-bit
s 16-bit
s 32-bit
U2, U2+, U3, U3+
s 8-bit
s 16-bit
s 32-bit
1 page  
Advisory
May 2001
TDAT042G5 Device Advisory
for Version 1 and 1A of the Device
Microprocessor Interface (MPU)
MPU1. Interface to Motorola* MC68360 Processor Is Not Glueless
The interface between the Motorola MC68360 processor and TDAT042G5 requires intervening logic because of
the following incompatibilities in the specifications of these two devices. For a 33 MHz microprocessor clock rate,
the Motorola MC68360 series processors can be interfaced to TDAT042G5 without intervening glue logic, if used
without DT and if programmed for six wait-states. If a user wishes not to use the wait-states, then the chip select
applied to TDAT042G5 must be held low until the address changes. Details are given below.
Chip Select Timing
The TDAT042G5 CS input signal requirements are not compatible with the Motorola MC68360 series processor
CSx output signals. TDAT042G5 timing does not allow simultaneous deassertion of CS and ADS signals. Chip
select applied to TDAT042G5 must be held low for at least 5 ns after the MC68360 deasserts ADS.
Workaround: Use external glue logic to decode the address to generate CS, or provide microprocessor interface
signals meeting the requirements of TDAT042G5.
DT Timing
If the Motorola MC68360 processor CSx signal is used to drive the TDAT042G5 CS, then TDAT042G5 DT output
does not satisfy the MC68360 processor DSACK timing requirement. DT is not pulled to 1 before it is placed in a
high-impedance state. This causes the next MPU cycle to be terminated early.
Workaround: Place a 1 kΩ resistor from DT to VDDD.
Corrective Action
Corrective action for MPU1 has not been determined.
MPU2. Synchronous Microprocessor Interface Mode Is Nonfunctional
The synchronous microprocessor interface mode, MPMODE = 1 (pin D8), functions as described in the advance
data sheet, but causes data errors. Placing TDAT042G5 in the synchronous mode and placing a clock on MPCLK
(pin C8) will cause the data passing through the device to be corrupted. Data errors are generated at a rate of 1%
or less of corrupted packets.
Workaround
Use the TDAT042G5 in the asynchronous microprocessor mode, MPMODE = 0, with no clock applied to MPCLK.
Corrective Action
This condition will be resolved in version 1A of the device.
* Motorola is a registered trademark of Motorola, Inc.
Agere Systems Inc.
3
5 Page 
Advisory
May 2001
TDAT042G5 Device Advisory
for Version 1 and 1A of the Device
Data Engine (DE) (continued)
DE5. Packet Behavior in POS/SDL Mode—Dry Mode
When the device is configured in POS mode with dry mode enabled, the following conditions may persist:
I PPP mode; STS-48/STS-12/STS-3.
When running in PPP mode, the PPP header—0xFF03 0x0021 (provisionable)—may be incorrectly inserted at
any point in a packet within the outgoing data stream when the FIFO runs dry, thereby corrupting the packet.
Packets being sent are corrupted if the FIFO runs dry.
I PPP and CRC modes; STS-48/STS-12/STS-3.
CRC, PPP, and HDLC modes; STS-48/STS-12/STS-3.
In PPP, CRC, and HDLC dry modes, some of the packet data may be corrupted when the packet length is above
a certain size where size is dependent upon UT clock rate and low watermark setting. Either sections of the
packet may be lost or additional packets may be inserted.
Workaround
Several workarounds are possible:
I Do not provision dry mode for this device.
I If dry mode is provisioned:
— Do not allow the FIFO to be emptied.
— Run the UTOPIA clock fast enough, as shown in Table 3, so that the FIFO is never empty.
— Use a larger external FIFO to buffer the data.
— Do not allow the packet size to exceed the low watermark.
Table 3. Required UTOPIA Clock (TxCLK) Rates
Mode
STS-48/STM-16
STS-12/STM-4
STS-3/STM-1
TxCLK and Rate
TxCLK > 77 MHz (U3+, 32-bit mode)
TxCLK > 40 MHz
TxCLK > 10 MHz
Corrective Action
This condition will be corrected in version 1A of the device.
Agere Systems Inc.
9
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