PDF TDA9801 Data sheet ( Hoja de datos )

Número de pieza	TDA9801
Descripción	Single standard VIF-PLL demodulator and FM-PLL detector
Fabricantes	NXP Semiconductors
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No Preview Available ! INTEGRATED CIRCUITS DATA SHEET TDA9801 Single standard VIF-PLL demodulator and FM-PLL detector Product speciﬁcation Supersedes data of 1998 May 06 File under Integrated Circuits, IC02 1999 Aug 26 1 page Philips Semiconductors Single standard VIF-PLL demodulator and FM-PLL detector Product speciﬁcation TDA9801 PINNING SYMBOL PIN DESCRIPTION VIF1 1 VIF differential input 1 VIF2 2 VIF differential input 2 TOP 3 tuner AGC TakeOver Point (TOP) connection ADJ 4 phase adjust connection MUTE 5 sound mute switch connection TPLL 6 PLL time constant connection CVBS 7 CVBS (positive) video output n.c. 8 not connected AF 9 AF output DAF 10 AF ampliﬁer decoupling capacitor connection SI 11 sound intercarrier input TAGC 12 tuner AGC output VSO 13 video and sound intercarrier output VI 14 buffer ampliﬁer video input AFC 15 AFC output VCO1 VCO2 GND 16 VCO1 reference circuit for 2fPC 17 VCO2 reference circuit for 2fPC 18 ground supply (0 V) AGC 19 AGC detector capacitor connection VP 20 supply voltage (+5 V) handbook, halfpage VIF1 1 VIF2 2 20 VP 19 AGC TOP 3 18 GND ADJ 4 17 VCO2 MUTE 5 TPLL 6 16 VCO1 TDA9801 15 AFC CVBS 7 14 VI n.c. 8 13 VSO AF 9 12 TAGC DAF 10 11 SI MHA880 Fig.2 Pin configuration. 1999 Aug 26 5 5 Page Philips Semiconductors Single standard VIF-PLL demodulator and FM-PLL detector Product speciﬁcation TDA9801 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT TUNER AGC OUTPUT: PIN TAGC Vmax maximum voltage Vsat saturation voltage Isink sink current from external source; − − 13.2 note 2 ITAGC = 1.7 mA − − 0.2 see Fig.6 no tuner gain reduction − 0.1 0.3 maximum tuner gain 1.7 2.0 2.6 reduction V V µA mA AFC detector: pin AFC; note 15 CRstps control steepness ∆f/∆T Vo frequency variation with temperature output voltage Io ∆Ir(v)(p-p) output current residual video modulation current (peak-to-peak value) equal to ∆IAFC/∆fVIF see Table 2 fPC = 38.9 MHz fPC = 45.75 MHz fPC = 58.75 MHz IAFC = 0; note 4 without external components; see Fig.8 upper limit lower limit see Fig.8 source current sink current −0.5 −0.75 −1.0 µA/kHz −0.4 −0.65 −0.9 µA/kHz −0.3 −0.55 −0.8 µA/kHz − − ±20 × 106 K−1 VP − 0.5 VP − 0.3 − − 0.3 0.5 150 200 250 150 200 250 − 20 30 V V µA µA µA Sound mute switch: pin MUTE; note 16 VIL VIH IIL αmute ∆Voffset(MUTE) LOW-level input voltage HIGH-level input voltage LOW-level input current mute attenuation DC offset voltage at pin MUTE mute on mute off VMUTE = 0 V VMUTE = 0 V at switching to mute on state (plop) 0 1.5 − 70 − − − −300 80 100 0.8 VP −360 − 500 V V µA dB mV FM sound limiter ampliﬁer input: pin SI; note 17 Vi(FM)(rms) FM input voltage (RMS value) “CCIR468-4” S/N = 40 dB; see Fig.10 αAM = 40 dB; f = 1 kHz; m = 0.3 − − 200 300 1− Vi(FM)(max)(rms) maximum FM input handling voltage (RMS value) 200 − − VI DC input voltage 2.3 2.6 2.9 µV mV mV V 1999 Aug 26 11 11 Page

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