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PDF TDA9143 Data sheet ( Hoja de datos )
| Número de pieza | TDA9143 | |
| Descripción | I2C-bus controlled/ alignment-free PAL/NTSC/SECAM decoder/sync processor | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
TDA9143
I2C-bus controlled, alignment-free
PAL/NTSC/SECAM decoder/sync
processor
Preliminary specification
File under Integrated Circuits, IC02
1996 Jan 17
1 page  
Philips Semiconductors
I2C-bus controlled, alignment-free
PAL/NTSC/SECAM decoder/sync processor
Preliminary specification
TDA9143
PINNING
SYMBOL
−(R−Y)
−(B−Y)
Uin
Vin
SCL
SDA
VCC
DEC
DGND
SC
VA
Yout
Vout
Uout
I/O PORT
O PORT/LLC
CLP/HA
F
B
G
R
ADDR (CVBS)
Fscomb
HPLL
C
Y/CVBS
AGND
FILTref
CPLL
XTAL
XTAL2
SECref
PIN DESCRIPTION
1 output signal for −(R−Y)
2 output signal for −(B−Y)
3 chrominance U input
4 chrominance V input
5 serial clock input
6 serial data input/output
7 positive supply voltage
8 digital supply decoupling
9 digital ground
10 sandcastle output
11 vertical acquisition
synchronization pulse
12 luminance output
13 chrominance V output
14 chrominance U output
15 input/output port
16 output port/line-locked clock
output
17 clamping pulse/HA
synchronization pulse
input/output
18 fast switch select input
19 BLUE input
20 GREEN input
21 RED input
22 I2C-bus address input (CVBS
output)
23 comb filter status input/output
24 horizontal PLL filter
25 chrominance input
26 luminance/CVBS input
27 analog ground
28 filter reference decoupling
29 colour PLL filter
30 reference crystal input
31 second crystal input
32 SECAM reference decoupling
handbook, halfpage
−(R−Y) 1
−(B−Y) 2
32 SECref
31 XTAL2
Uin 3
Vin 4
SCL 5
SDA 6
30 XTAL
29 CPLL
28 FILTref
27 AGND
VCC 7
DEC 8
DGND 9
26 Y/CVBS
25 C
TDA9143
24 HPLL
SC 10
23 Fscomb
VA 11
22 ADDR (CVBS)
Yout 12
Vout 13
Uout 14
I/O PORT 15
21 R
20 G
19 B
18 F
O PORT/LLC 16
17 CLP/HA
MGE038
Fig.2 Pin configuration.
1996 Jan 17
5
5 Page 
Philips Semiconductors
I2C-bus controlled, alignment-free
PAL/NTSC/SECAM decoder/sync processor
Preliminary specification
TDA9143
When the controller is in the NEAR_NORM state it will
move to the COUNT state if it detects the vertical sync
pulse within the NEAR_NORM window (i.e.
622 < LC < 628). If no vertical sync pulse is detected the
controller will move back to the COUNT state when the line
counter reaches LC = 628. The line counter will then be
reset.
When the controller is in the NO_NORM state, it will move
to the COUNT state when it detects a vertical sync pulse
and reset the line counter. If a vertical sync pulse is not
detected before LC = 722 (if the ϕ1 loop is locked in forced
mode) it will move to the COUNT state and reset the line
counter. If the ϕ1 loop is not locked the controller will return
to the COUNT state when LC = 628.
The forced mode option keeps the controller in either the
left-hand side (60 Hz) or the right-hand side (50 Hz) of the
state diagram.
Figure 6 illustrates the state diagram of the norm counter
which is an up/down counter that increases its counter
value by 1 if it finds a vertical sync pulse within the selected
window. If not, it decreases the counter value by 1 (or 2,
see Fig.6). In the NEAR_NORM and NORM states the first
correct vertical sync pulse after one or more incorrect
vertical sync pulses is processed as an incorrect pulse.
This procedure prevents the system from staying in the
NEAR_NORM or NORM state if the vertical sync pulse is
correct in the first field and incorrect in the second field.
In case of no sync lock (SLN = 1) the norm counter is reset
to NO_NORM (wide search window), for fast vertical
catching when switching between video sources. Fast
switching between different channels however can still
result in a continuous horizontal sync lock situation, when
the channel is changed before the norm counter has
reached the NORM state. To provide faster vertical
catching in this case, measures have been taken to
prevent the norm counter to count down to zero before
reaching the NO_NORM state (see left-hand of Fig.6). Bus
bit FWW (forced wide window) enables the norm counter
to stay in the NO_NORM state if desired. The
norm/no_norm status is read out by bus bit NRM.
handbook, full pagewidth
22 < NC ≤ 27
0 ≤ NC < 12
NORM
NC = 22
(RESET NC)
NO
NORM
NC = 26
10 < NC < 26(1)
NEAR
NORM
(NRCES=E1T0 NC)
NC = 0 NC = 12
NC = 17
NEAR
NORM
10 < NC < 17
NC = 14
NEAR
NORM
0 < NC < 14
norm test area
near_norm test area MGE041
(1) VSP found: count 1 up; no VSP found: count 2 down.
Fig.6 State diagram of the norm counter.
1996 Jan 17
11
11 Page | ||
| Páginas | Total 40 Páginas | |
| PDF Descargar | [ Datasheet TDA9143.PDF ] | |
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