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PDF TDA9116 Data sheet ( Hoja de datos )
| Número de pieza | TDA9116 | |
| Descripción | LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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TDA9116
LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR
FOR MULTISYNC MONITOR
FEATURES
General
s ADVANCED I2C BUS CONTROLLED
DEFLECTION PROCESSOR DEDICATED
FOR HIGH-END CRT MONITORS
s SINGLE SUPPLY VOLTAGE 12V
s VERY LOW JITTER
s DC/DC CONVERTER CONTROLLER
s ADVANCED EW DRIVE
s ADVANCED ASYMMETRY CORRECTIONS
s AUTOMATIC MULTISTANDARD
SYNCHRONIZATION
s VERTICAL DYNAMIC CORRECTION
WAVEFORM OUTPUT
s X-RAY PROTECTION AND SOFT-START &
STOP ON HORIZONTAL AND DC/DC DRIVE
OUTPUTS
s I2C BUS STATUS REGISTER
Horizontal section
s 150 kHz maximum frequency
s Corrections of geometric asymmetry:
Pin cushion asymmetry, Parallelogram
s Tracking of asymmetry corrections with vertical
size and position
s Fully integrated internal horizontal moiré
cancellation and moiré cancellation output
Vertical section
s 200 Hz maximum frequency
s Vertical ramp for DC-coupled output stage with
adjustments of: C-correction, S-correction for
super-flat CRT, Vertical size, Vertical position
s Vertical moiré cancellation through vertical
ramp waveform
s Compensation of vertical breathing with EHT
variation
EW section
s Symmetrical geometry corrections: Pin cushion,
Keystone, Top/Bottom corners separately
s Horizontal size adjustment
s Tracking of EW waveform with Vertical size and
position and adaptation to frequency
s Compensation of horizontal breathing through
EW waveform
September 2003
Dynamic correction section
s Output with vertical dynamic correction
waveform for dynamic corrections like focus,
brightness uniformity, ...
s Fixed on screen by means of tracking system
DC/DC controller section
s Step-up and step-down conversion modes
s External sawtooth configuration
s Bus-controlled output voltage
s Synchronization on hor. frequency with phase
selection
s Selectable polarity of drive signal
DESCRIPTION
The TDA9116 is a monolithic integrated circuit as-
sembled in a 32-pin shrink dual-in-line plastic
package. This IC controls all the functions related
to horizontal and vertical deflection in multimode
or multi-frequency computer display monitors.
The internal sync processor, combined with the
powerful geometry correction block, makes the
TDA9116 suitable for very high performance mon-
itors, using few external components.
Combined with other ST components dedicated
for CRT monitors (microcontroller, video preampli-
fier, video amplifier, OSD controller) the TDA9116
allows fully I2C bus-controlled computer display
monitors to be built with a reduced number of ex-
ternal components.
ORDERING INFORMATION
Ordering code
TDA9116
Package
Shrink 32 (plastic)
Version 4.0
1/47
1
1 page  
2 - PIN CONFIGURATION
H/HVSyn
VSyn
HLckVBk
HOscF
HPLL2C
CO
HGND
RO
HPLL1F
HPosF
HMoiré
HFly
RefOut
BComp
BRegIn
BISense
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VDyCor
31 SDA
30 SCL
29 Vcc
28 BOut
27 GND
26 HOut
25 XRay
24 EWOut
23 VOut
22 VCap
21 VGND
20 VAGCCap
19 VOscF
18 VEHTIn
17 HEHTIn
TDA9116
5/47
5 Page 
TDA9116
7.4 - HORIZONTAL SECTION
Vcc = 12V, Tamb = 25°C
Symbol
PLL1
IRO
CCO
fHO
fHO(0)
fHOCapt
Parameter
Test Conditions
Min.
Current load on RO pin
Capacitance on CO pin
Frequency of hor. oscillator
Free-running frequency of hor. oscill. (1)
Hor. PLL1 capture frequency (4)
RRO=5.23kΩ, CCO=820pF
fHO(0) = 28.5kHz
390
27
29
Value
Typ.
28.5
Max.
1.5
150
29.9
122
Units
mA
pF
kHz
kHz
kHz
----∆----f--H----O-----(--0---)----
fHO(0) ⋅ ∆T
Temperature drift of free-running freq. (3)
-150
ppm/°C
∆fHO/∆VHO
VHO
VHOThrfr
Average horizontal oscillator sensitivity fHO(0) = 28.5kHz
H. oscill. control voltage on pin HPLL1F VRefO=8V
Threshold on H. oscill. control voltage on
HPLL1F pin for tracking of EW with freq.
VRefO=8V
VHPosF
VHOThrLo
VHOThrHi
PLL2
RIn(HFly)
IInHFly
VThrHFly
VS(0)
VBotHPLL2C
VTopHPLL2C
tph(min)/TH
Control voltage on HPosF pin
Bottom of hor. oscillator sawtooth(6)
Top of hor. oscillator sawtooth(6)
HPOS (Sad01):
1111111xb
1000000xb
0000000xb
Input impedance on HFly input
Current into HFly input
V(HFly) >VThrHFly (2)
At top of H flyback pulse
Voltage threshold on HFly input
H flyback lock middle point(6)
No PLL2 phase modula-
tion
Low clamping voltage on HPLL2C pin(5)
High clamping voltage on HPLL2C pin(5)
Min. advance of H-drive OFF before
middle of H flyback(7)
Null asym. correction
tph(max)/TH
Max. advance of H-drive OFF before
middle of H flyback(8)
Null asym. correction
H-drive output on pin HOut
IHOut
tHoff/TH
Current into HOut output
Duty cycle of H-drive signal
Output driven LOW
HDUTY (Sad00):
x1111111b
x0000000b
Soft-start/Soft-stop value
Picture geometry corrections through PLL1 & PLL2
tHph/TH
H-flyback (center) static phase vs. sync
signal (via PLL1), see Figure 7
HPOS (Sad01):
1111111xb
0000000xb
1.4
300
0.6
19.6
5.0
2.8
3.4
4.0
1.6
6.4
500
0.7
4.0
1.6
4.0
0
44
27
65
85
+11
-11
kHz/V
6.0 V
V
V
V
V
V
V
700 Ω
5 mA
V
V
V
V
%
%
30 mA
%
%
%
%
%
11/47
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TDA9116.PDF ] | |
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