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PDF TDA9112 Data sheet ( Hoja de datos )
| Número de pieza | TDA9112 | |
| Descripción | LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR | |
| Fabricantes | ST Microelectronics | |
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TDA9112
LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR
FOR MULTISYNC MONITOR
FEATURES
General
s ADVANCED I2C BUS CONTROLLED
DEFLECTION PROCESSOR DEDICATED
FOR HIGH-END CRT MONITORS
s SINGLE SUPPLY VOLTAGE 12V
s VERY LOW JITTER
s DC/DC CONVERTER CONTROLLER
s ADVANCED EW DRIVE
s ADVANCED ASYMMETRY CORRECTIONS
s AUTOMATIC MULTISTANDARD
SYNCHRONIZATION
s 2 DYNAMIC CORRECTION WAVEFORM
OUTPUTS
s X-RAY PROTECTION AND SOFT-START &
STOP ON HORIZONTAL AND DC/DC DRIVE
OUTPUTS
s I2C BUS STATUS REGISTER
Horizontal section
s 150 kHz maximum frequency
s Corrections of geometric asymmetry: Pin
cushion asymmetry, Parallelogram, separate
Top/Bottom corner asymmetry
s Tracking of asymmetry corrections with vertical
size and position
s Fully integrated horizontal moiré cancellation
Vertical section
s 200 Hz maximum frequency
s Vertical ramp for DC-coupled output stage with
adjustments of: C-correction, S-correction for
super-flat CRT, Vertical size, Vertical position
s Vertical moiré cancellation through vertical
ramp waveform
s Compensation of vertical breathing with EHT
variation
EW section
s Symmetrical geometry corrections: Pin cushion,
Keystone, Top/Bottom corners separately
s Horizontal size adjustment
s Tracking of EW waveform with Vertical size and
position and adaptation to frequency
s Compensation of horizontal breathing through
EW waveform
November 2001
Dynamic correction section
s Generates waveforms for dynamic corrections
like focus, brightness uniformity, ...
s 1 output with vertical dynamic correction
waveform
s 1 output with composite HV dynamic correction
waveform
s Fixed on screen by means of tracking system
DC/DC controller section
s Step-up and step-down conversion modes
s Internal and external sawtooth configurations
s Bus-controlled output voltage
s Synchronization on hor. frequency with phase
selection
s Selectable polarity of drive signal
DESCRIPTION
The TDA9112 is a monolithic integrated circuit as-
sembled in a 32-pin shrink dual-in-line plastic
package. This IC controls all the functions related
to horizontal and vertical deflection in multimode
or multi-frequency computer display monitors.
The internal sync processor, combined with the
powerful geometry correction block, makes the
TDA9112 suitable for very high performance mon-
itors, using few external components.
Combined with other ST components dedicated
for CRT monitors (microcontroller, video preampli-
fier, video amplifier, OSD controller) the TDA9112
allows fully I2C bus-controlled computer display
monitors to be built with a reduced number of ex-
ternal components.
SHRINK 32 (Plastic Package)
ORDER CODE: TDA9112
Version 4.2
1/51
1
1 page  
H/HVSyn 1
HLckVBk 3
SDA 31
SCL 30
Vcc 29
RefOut 13
GND 27
HGND
7
HPosF
10
HPLL1F
9
R0 C0 HOscF
864
HFly
12
HPLL2C
5
H-sync
detection
Polarity
handling
V-blank
H-lock
I2C Bus
interface
Phase/frequency
comparator
Horizontal position
Lock detection
Horizontal
VCO
PLL1
H-moiré controller
H-moiré amplitude
I2C Bus registers
: Functions controlled via I2C Bus
Phase comparator
Phase shifter
H duty controller
Pin cushion asymm.
Parallelogram
Top corner asymm.
Bottom corner asymm.
Hor. duty cycle
PLL2
H-drive
buffer
Safety
processor
B+
DC/DC
converter
controller
B+ ref.
Supply
supervision
Reference
generation
V-sync
extraction
& detection
V-dynamic
correction
(focus, bright.)
VDyCor amplitude
Geometry
tracking
HV-dynamic
correction
(focus,brightness)
HVDyCor V-amplitude
HVDyCor H-amplitude
HVDyCor H-symmetry
Internal
ref.
V-sync detection
Input selection
Polarity handling
Vertical oscillator
with AGC
S-correction
C-correction
V-ramp control
Tracking EHT
Vertical size
Vertical position
Vertical moiré
EW generator
H size
Pin cushion
Keystone
Top corners
Bottom corners
26 HOut
25 XRay
28 BOut
16 BIsense
15 BRegIn
14 BComp
11 HVDyCor
24 EWOut
2
VSyn
21
VGND
19 20 22
32
VOscF
VCap VDyCor
VAGCCap
23
VOut
18
VEHTIn
17
HEHTIn
TDA9112
5 Page 
TDA9112
Symbol
Parameter
Test Condit ions
Value
Units
Min. Typ. Max.
tPCAC/TH
Contribution of pin cushion asymmetry
correction to phase of H-drive vs. static
phase (via PLL2), measured in corners
PCAC (Sad11h) full span
(9)
VPOS at medium
VSIZE at minimum
VSIZE at medium
VSIZE at maximum
± 1.0
± 1.8
± 2.8
%
%
%
PARAL (Sad12h) full span
(9)
tParalC/TH
Contribution of parallelogram correction
to phase of H-drive vs. static phase (via
PLL2), measured in corners
VPOS at medium
VSIZE at minimum
VSIZE at medium
VSIZE at maximum
VPOS at max. or min.
VSIZE at minimum
±1.75
± 2.2
± 2.8
±1.75
%
%
%
%
tTCAC/TH
Contribution of top corner asymmetry
correction to phase of H-drive vs. static
phase (via PLL2), measured in corners
TCAC (Sad13h) full
span(9)
VPOS at medium
VSIZE at minimum
VSIZE at medium
VSIZE at maximum
± 0.8
± 2.0
± 4.4
%
%
%
tBCAC/TH
Contribution of bottom corner asymmetry
correction to phase of H-drive vs. static
phase (via PLL2), measured in corners
BCAC (Sad14h) full
span(9)
VPOS at medium
VSIZE at minimum
VSIZE at medium
VSIZE at maximum
± 0.8
± 2.0
± 4.4
%
%
%
Note 1: Frequency at no sync signal condition. For correct operation, the frequency of the sync signal applied must
always be higher than the free-running frequency. The application must consider the spread of values of real
electrical components in RRO and CCO positions so as to always meet this condition. The formula to calculate
the free-running frequency is fHO(0)=0.12125/(RRO CCO)
Note 2: Base of NPN transistor with emitter to ground is internally connected on pin HFly through a series resistance of
about 500Ω and a resistance to ground of about 20kΩ.
Note 3: Evaluated and figured out during the device qualification phase. Informative. Not tested on every single unit.
Note 4: This capture range can be enlarged by external circuitry.
Note 5: The voltage on HPLL2C pin corresponds to immediate phase of leading edge of H-drive signal on HOut pin with
respect to internal horizontal oscillator sawtooth. It must be between the two clamping levels given. Voltage
equal to one of the clamping values indicates a marginal operation of PLL2 or non-locked state.
Note 6: Internal threshold. See Figure 6.
Note 7: The tph(min)/TH parameter is fixed by the application. For correct operation of asymmetry corrections through
dynamic phase modulation, this minimum must be increased by maximum of the total dynamic phase required
in the direction leading to bending of corners to the left. Marginal situation is indicated by reach of VTopHPLL2C
high clamping level by waveform on pin HPLL2C. Also refer to Note 5 and Figure 6.
Note 8: The tph(max)/TH parameter is fixed by the application. For correct operation of asymmetry corrections through
dynamic phase modulation, this maximum must be reduced by maximum of the total dynamic phase required in
the direction leading to bending of corners to the right. Marginal situation is indicated by reach of VBotHPLL2C
low clamping level by waveform on pin HPLL2C. Also refer to Note 5 and Figure 6.
Note 9: All other dynamic phase corrections of picture asymmetry set to their neutral (medium) positions.
11/51
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TDA9112.PDF ] | |
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