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PDF TDA9103 Data sheet ( Hoja de datos )
| Número de pieza | TDA9103 | |
| Descripción | DEFLECTION PROCESSOR FOR MULTISYNC MONITOR | |
| Fabricantes | ST Microelectronics | |
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TDA9103
DEFLECTION PROCESSOR FOR MULTISYNC MONITOR
HORIZONTAL
. DUAL PLL CONCEPT
. 150kHz MAXIMUM FREQUENCY
. SELF-ADAPTIVE (EX : 30 TO 85kHz)
. X-RAY PROTECTION INPUT
. DC ADJUSTABLE DUTY-CYCLE
. INTERNAL 1st PLL LOCK/UNLOCK IDENTIFICA-
TION
. 4 OUTPUTS FOR S-CORRECTION
. WIDE RANGE DC CONTROLLED H-POSITION
. ON/OFF SWITCH (FOR PWR MANAGEMENT)
. TWO H-DRIVE POLARITIES
VERTICAL
. VERTICAL RAMP GENERATOR
. 50 TO 150Hz AGC LOOP
. DC CONTROLLED V-AMP, V-POS, S-AMP AND S-
CENTERING
. ON/OFF SWITCH
B+ REGULATOR
. INTERNAL PWM GENERATOR FOR B+ CURRENT
MODE STEP-UP CONVERTER
. DC ADJUSTABLE B+ VOLTAGE
. OUTPUT PULSES SYNCHRONISED ON HORIZON-
TAL FREQUENCY
. INTERNAL MAXIMUM CURRENT LIMITATION
.EWPCC
VERTICAL PARABOLA GENERATOR WITH DC
CONTROLLED KEYSTONE AND AMPLITUDE
GENERAL
. ACCEPT POS. OR NEG. H AND V SYNC POLARI-
TIE S
. SEPARATED H AND V TTL INPUT
. SAFETY BLANKING OUTPUT
DESCRIPTION
The TDA9103 is a monolithic integrated circuit assembled
in a 42 pins shrunk dual in line plastic package.
This IC controls all the functions related to the horizontal
and vertical deflection in multimodes or multisync monitors.
As can be seen in the block diagram, the TDA9103 includes
the following functions :
- Positive or Negative sync polarities,
- Auto-sync horizontal processing,
- H-PLL lock/unlock identification,
- Auto-sync Vertical processing,
- East/West signal processing block,
- B+ controller,
- Safety blanking output.
May 1996
T his IC, combined with TDA9205 (RG B preamp),
STV9420/21 or 22 (O.S.D. processor), ST7271 (micro
controller) and TDA8172 (vertical booster), allows to real-
ize very simple and high quality multimodes or multisync
monitors.
SHRINK42
(Plastic Package)
ORDER CODE : TDA9103
PIN CONNECTIONS
PLL2C
H-DUTY
HFLY
HGND
HREF
S4
S3
S2
S1
C0
R0
PLL1F
HLOCK-CAP
FH-MIN
H-POS
XRAY-IN
HSYNC
VCC
GND
H-OUTEM
H-OUTCOL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42 ISENSE
41 COMP
40 REGIN
39 B+-ADJ
38 KEYST
37 E/W-AMP
36 E/WOUT
35 PLL1INHIB
34 VSYNC
33 V-POS
32 VDCOUT
31 V-AMP
30 VOUT
29 VS-CENT
28 VS-AMP
27 VCAP
26 VREF
25 VAGCCAP
24 VGND
23 SBLKOUT
22 B+OUT
1/27
1 page  
TDA9103
ABSOLUTE MAX RATING
Symbol
VCC
VIN
VESD
Tstg
Tj
Toper
Parameter
Supply Voltage (Pin 18)
Max Voltage on
Pins 2, 14, 15, 28, 29, 31, 33, 37, 38, 39
Pin 3
Pins 17, 34
Pin 40
Pin 42
Pin 16
ESD Succeptibility
Human Body Model, 100pF Discharge through 1.5kΩ
EIAJ Norm, 200pF Discharge through 0Ω
Storage Temperature
Max Operating Junction Temperature
Operating Temperature
Value
13.5
8
1.8
6
8
8
5.5
2
300
-40, +150
150
0, +70
Unit
V
V
kV
V
°C
°C
°C
THERMAL DATA
Symbol
Rth (j-a)
Parameter
Junction-Ambient Thermal Resistance
HORIZONTAL SECTION
Operating conditions
Symbol
Parameter
VCO
R0min Oscillator Resistor Min Value
C0min
Fmax
Oscillator Capacitor Min Value
Maximum Oscillator Frequency
HsVR Horizontal Sync Input Voltage Range
INPUT SECTION
MinD
Mduty
Minimum Input Pulses Duration
Maximum Input Signal Duty Cycle
OUTPUT SECTION
I3m
IS1 to IS4
VS1 to VS4
Maximum Input Peak Current on Pin 3
Maximum Current on S1 to S4 Outputs
Maximum Voltage on S1 to S4 Outputs
HOI1
HOI2
Horizontal Drive Output Max Current
Horizontal Drive Output Max Current
DC CONTROL VOLTAGES
DCadj DC Voltage Range on DC Controls
Max.
Value
65
Unit
°C/W
Test conditions
Min. Typ. Max. Unit
Pin 11
Pin 10
Pin 17
6 kΩ
390 pF
150 kHz
0 5.5 V
Pin 17
Pin 17
0.7 µS
25 %
Pins 6 to 9
Pins 6 to 9
Pin 20, sourced current
Pin 21, sunk current
2 mA
0.5 mA
VCC V
20 mA
20 mA
VREF-H = 8V, Pins 2-14-15
2
6V
5/27
5 Page 
TDA9103
OPERATING DESCRIPTION
GENERAL CONSIDERATIONS
Power Supply
The typical value of the power supply voltage VCC
is 12V. Perfect operation is obtained if VCC is main-
tained in the limits : 10.8V → 13.2V.
In order to avoid erratic operation of the circuit
during the transient phase of VCC switching on, or
switching off, the value of VCC is monitored and the
outputs of the circuit are inhibited if it is too low.
In order to have a very good powersupplyrejection,
the circuit is internally powered by several internal
voltage references (The unique typical value of
which is 8V). Two of these voltage references are
externally accessible, one for the vertical part and
one for the horizontal part. These voltage refer-
ences can be used for the DC control voltages
applied on the concerned pins by the way of poten-
tiometers or digital to analog converters (DAC’s).
Furthermore it is possible to filter the a.m. voltage
references by the use of external capacitor con-
nected to ground, in order to minimize the noise
and consequently the ”jitter” on vertical and hori-
zontal output signals.
DC Control Adjustments
The circuit has 10 adjustment capabilities : 3 for the
horizontal part, 1 for the SMPS part, 2 for the E/W
correction, 4 for the vertical part.
The corresponding inputs of the circuit has to be
driven with a DC voltage typically comprised be-
tween 2 and 6V for a value of the internal voltage
reference of 8V.
More precisely, the control voltages have to be
maintained between VREF/4 and 3/4 ⋅ VREF. The
application of control voltages outside this range is
not dangerousfor the circuit but the good operation
is not guaranted (except for Pin 2 : duty cycle
adjusment. See outputs inhibition paragraph).
Figure 5 :
Example of Practical DC Control
Voltage Generation
VREF
10kΩ
22kΩ
DC Control Voltage
10kΩ
The input currents of the DC control inputs are
typically very low (about a few µA). Depending on
the internal structure of the inputs, the input cur-
rents can be positive or negative (sink or source).
HORIZONTAL PART
Input section
The horizontal input is designed to be sensitive to
TTL signals typically comprised between 0 and 5V.
The typical threshold of this input is 1.6V. This input
stage uses an NPN differential stage and the input
current is very low.
Concerning the duty cycle of the input signal, the
following signals may be applied to the circuit.
Figure 6
Z
T
Z
Using internal integration, both signals are recog-
nized on condition that Z/T ≤ 25%. Synchronisation
occurs on the leading edge of the rectified signal.
The minimum value of Z is 0.7µs.
Figure 7 : Input Structure
HSYNC
1.6V
PLL1
The PLL1 is composed of a phase comparator, an
external filter and a Voltage Controlled Oscillator
(VCO).
The phase comparatoris a ”phase frequency” type,
designed in CMOS technology. This kind of phase
detector avoids locking on false frequencies. It is
followed by a ”charge pump”, composed of 2 cur-
rent sources sink and source (I = 1mA typ.)
11/27
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet TDA9103.PDF ] | |
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