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PDF TDA8960 Data sheet ( Hoja de datos )
| Número de pieza | TDA8960 | |
| Descripción | ATSC 8-VSB demodulator and decoder | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
TDA8960
ATSC 8-VSB demodulator and
decoder
Preliminary specification
File under Integrated Circuits, IC02
1999 Jun 14
1 page  
Philips Semiconductors
ATSC 8-VSB demodulator and decoder
BLOCK DIAGRAM
Preliminary specification
TDA8960
handbook, full pagewidth
EQLOCKINDIC
LOCKINDIC
53 54
LOCK
DETECTORS
AGCOUT
56
ADIN0 to ADIN9
1 to 8, 11, 12
RESET
27
RSTAN
DIGITAL FRONT-END(1)
61
TRSDO
SERIAL
62
TRSTB
DAC
63
INTERFACE
TRCS
64
TRLD
TRELLIS DECODER
TDA8960
SYNCHRO-
NIZATION
DE-INTERLEAVER
REED SOLOMON DECODER
17
TDI
21
TDO
BOUNDARY
SCAN TEST
20
18
TRST
TMS
19
TCK
DE-RANDOMIZER
FIFO
13
A0
16
I2C-BUS
A1
14
INTERFACE
SCL
15
SDA
23, 34, 30, 38,
31 to 33
45, 57, 49,55,
35 to 37
9, 26,
10, 28,
59
29
39, 40 22 24 25
41, 60
42, 58
CLK
DATACLK
ERROR SOP DATAVALID VSSD1 to VSSD8
DATA7 to DATA0
VDDD1 to VDDD8
MGR598
(1) The digital front-end consists of the following circuits:
- Fine AGC
- Carrier recovery
- Half Nyquist filter
- Symbol timing recovery
- Sync recovery and pilot removal
- Adaptive equalization.
Fig.1 Block diagram.
1999 Jun 14
5
5 Page 
Philips Semiconductors
ATSC 8-VSB demodulator and decoder
Preliminary specification
TDA8960
DAC interface
The TDA8960 D/A interface connects to an external off-chip serial D/A converter. It supports four different serial modes.
EXTERNAL INTERFACE
The DAC interface consists of pins 61 to 64; see Table 2.
Table 2 DAC interface
PIN
TRSDO
TRSTB
TRCS
TRLD
FUNCTION
serial data output
strobe signal which can be used by the DAC to shift in serial data
chip select signal for DAC is also used by some DACs to load serially shifted data in the internal
parallel register on the positive edge
load signal used by some DACs to load serially shifted data in the internal parallel latches
OUTPUT MODES
Table 3 shows which DACs can be used in the different output modes.
Table 3 DAC serial interface modes and DAC types
OUTPUT MODE
0
1
2
3
POLARITY
+dF/dV
+dF/dV
+dF/dV
−dF/dV
SET-UP TIME (ns)
EXAMPLE DEVICE
67 Maxim
MAX531, MAX538, MAX539, MAX504 and MAX515
Texas Instruments TLC5615
Sipex SP9500 and SP960
Linear Technology TLC1451
45 Analog Devices AD7943
45 Analog Devices DAC8512
67 same types as mode 0
The operating mode is programmed by means of the I2C-bus interface. Bits 4 and 5 of registers 09H control the mode;
see Table 13.
The timing diagrams of the different serial modes are shown in Fig.4. Modes 0 and 3 do not use the load signal available
at pin TRLD. In mode 3 the output of the timing recovery low-pass filter is inverted to control VCXOs which have a
negative dF/dV. Modes 0 and 3 can provide up to 67 ns of the serial data set-up time from the moment the TRSDO output
has a new data bit until the start of the TRSTB pulse.
In mode 1 the TRCS pin is not used.
1999 Jun 14
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TDA8960.PDF ] | |
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