PDF TDA8798 Data sheet ( Hoja de datos )

Número de pieza	TDA8798
Descripción	Dual 8-bit/ 100 Msps A/D converter with DPGA
Fabricantes	NXP Semiconductors
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No Preview Available ! INTEGRATED CIRCUITS DATA SHEET TDA8798 Dual 8-bit, 100 Msps A/D converter with DPGA Objective speciﬁcation Supersedes data of 1998 Apr 15 File under Integrated Circuits, IC02 1999 Sep 16 1 page Philips Semiconductors Dual 8-bit, 100 Msps A/D converter with DPGA SYMBOL BUF1 BUF1N Voref1 VDDA3 VSSA3 CLK1N CLK1 VSSD1 VDDD1 SMODE SEN2 SDATA SCLK SEN1 VDDO1 VSSO1 A7 A6 A5 A4 A3 A2 A1 A0 B0 B1 B2 B3 B4 B5 B6 B7 VSSO2 VDDO2 OE SR DPGAEN TEST TE VDDD2 VSSD2 1999 Sep 16 PIN DESCRIPTION 17 buffer1 non-inverting input 18 buffer1 inverting input 19 buffer1 common mode reference output 20 ADC1 analog supply voltage 3 21 ADC1 analog ground 3 22 ADC1 inverting clock input 23 ADC1 non-inverting clock input 24 digital ground 1 25 digital supply voltage 1 26 serial interface mode input 27 serial interface enable 2 (active low) 28 serial interface data input 29 serial interface clock input 30 serial interface enable 1 (active low) 31 output stage supply voltage 1 32 output stage ground 1 33 channel 1 output bit 7 (MSB) 34 channel 1 output bit 6 35 channel 1 output bit 5 36 channel 1 output bit 4 37 channel 1 output bit 3 38 channel 1 output bit 2 39 channel 1 output bit 1 40 channel 1 output bit 0 (LSB) 41 channel 2 output bit 0 (LSB) 42 channel 2 output bit 1 43 channel 2 output bit 2 44 channel 2 output bit 3 45 channel 2 output bit 4 46 channel 2 output bit 5 47 channel 2 output bit 6 48 channel 2 output bit 7 (MSB) 49 output stage ground 2 50 output stage supply voltage 2 51 digital output enable (active LOW) 52 digital output bit slew-rate control 53 DPGA enable (active LOW) 54 test input (to be grounded) 55 track-and-hold enable (active LOW) 56 digital supply voltage 2 57 digital ground 2 5 Objective speciﬁcation TDA8798 5 Page Philips Semiconductors Dual 8-bit, 100 Msps A/D converter with DPGA Objective speciﬁcation TDA8798 SYMBOL PARAMETER CONDITIONS MIN. BANDWIDTH AND SETTLING B(−3dB)(DPGA) DPGA −3 dB bandwidth tst settling time at Vi(dif)(max) full-scale transition 10% to 90% td(g) group delay fi up to 15 MHz at G(min) at G(max) GAIN G(min) G(max) Gstep Gstep(L) G(m)(c-c) ∆G/∆T ∆G/∆VDD minimum gain setting maximum gain setting gain step size gain step size linearity (actual gain step/average − 1) channel-to-channel gain matching ampliﬁer gain stability as a function of temperature at G(min) at G(max) at G(min) at G(max) ampliﬁer gain stability as a function of power supply voltage at G(min) at G(max) GAIN SWITCHING; TAMB = 25 °C tst(G-G) settling time between two consecutive gain settings CL = 68 pF tPD propagation delay REJECTION PSRR CMRR power supply rejection ratio DC to 15 MHz common mode rejection ratio at G(min) HARMONICS; TAMB = 25 °C HD2 second harmonic distortion fi = 15 MHz; at Vo(dif)(max); at gain control register: 00H 20H 3FH HD3 third harmonic distortion fi = 15 MHz; at Vo(dif)(max); at gain control register: 00H 20H 3FH 30 40 − − tbf tbf − −0.75 − − − − − − − − 40 40 40 40 − tbf tbf − TYP. tbf − tbf tbf 0 34 0.54 − tbf tbf 8 8 0.4 0.8 160 − − − tbf tbf tbf 50 50 50 MAX. UNIT − MHz − ns − ps − ps tbf dBV tbf dBV − dBV +0.75 dBV − dB − dB tbf mdB/°C tbf mdB/°C tbf dB/V tbf dB/V − ns 20 ns − dB − dB − dB − dB − dB − dB − dB − dB 1999 Sep 16 11 11 Page

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